Home > Samsung > Processor > Samsung Exynos 5 User Manual

Samsung Exynos 5 User Manual

    Download as PDF Print this page Share this page

    Have a look at the manual Samsung Exynos 5 User Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 1705 Samsung manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.

    Page
    of 881
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-8  
    13.3.8 Flowcharts of Operations in Each Mode 
    Execute these steps before any I2C Tx/Rx operations: 
    1. When required, write own slave address on I2CADD register 
    2. Set I2CCON register: 
     a)  Enable interrupt 
     b)  Define SCL period 
    3. Set I2CSTAT to enable Serial Output 
    Figure 13-6 illustrates operations in Master/Transmitter mode. 
     
        Figure 13-6   Operations in Master/Transmitter Mode W rite slave address to
    I2CDS.
    W rite 0xF0 (M/T Start)
    to I2CSTAT.
    The data of the I2CDS
    is transmitted.
    After ACK period
    interrupt is pending.
    W rite 0xD0 (M/T Stop)
    to I2CSTAT.
    W rite new data
    transmitted to I2CDS.
    Stop?
    Clear pending bit to
    resume.
    The data of the I2CDS
    is shifted to SDA.
    START
    Master Tx mode has
    been configured.
    Clear pending bit.
    W ait until the stop
    condition takes effect.
    END
    Y
    N  
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-9  
    NOTE: When Master transmit mode, stop sequence of I2C_HDMI and I2C_SATAPHY is as follows  
    Write 0xD0 to I2CSTAT  clear pending bit  Wait until the stop condition take effect  
     Write 0xC0 to I2CSTAT  END 
       
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-10  
    Figure 13-7 illustrates operations in Master/Receiver mode. 
     
        Figure 13-7   Operations in Master/Receiver Mode 
    NOTE: When Master receiver mode, stop sequence of I2C_HDMI and I2C_SATAPHY is as follows  
    Write 0x90 to I2CSTAT  clear pending bit  Wait until the stop condition take effect  
     Write 0x80 to I2CSTAT  END 
     
     Write slave address to
    I2CDS.
    Write 0xB0 (M/R Start)
    to I2CSTAT.
    The data of the I2CDS
    (Slave address) is transmitted.
    After ACK period
    interrupt is pending.
    Write 0x90 (M/R Stop)
    to I2CSTAT.
    Read a new data from
    I2CDS.
    Stop?
    Clear pending bit to
    resume.
    SDA is shifted to I2CDS.
    START
    Master Rx mode has
    been configured.
    Clear pending bit.
    Wait until the stop
    condition takes effect.
    END
    Y
    N  
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-11  
    Figure 13-8 illustrates operations in Slave/Transmitter mode. 
     
        Figure 13-8   Operations in Slave/Transmitter Mode 
     I2C detects start signal. and, I2CDS
    receives data.
    I2C compares I2CADD and I2CDS
    (the received slave address).
    W rite data to I2CDS.
    Clear pending bit to
    resume.
    The data of the I2CDS
    is shifted to SDA.
    START
    Slave Tx mode has
    been configured.
    END
    Matched?
    N
    Y
    Stop?
    Interrupt is pending.
    N
    Y
     
    The I2C address match
    interrupt is generated.  
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-12  
    Figure 13-9 illustrates operations in Slave/Receiver mode. 
     
        Figure 13-9   Operations in Slave/Receiver Mode 
     I2C detects start signal. and, 12CDS
    receives data.
    I2C compares I2CADD and I2CDS
    (the received slave address).
    Read data from I2CDS.
    Clear pending bit to
    resume.
    SDA is shifted to I2CDS.
    START
    Slave Rx mode has
    been configured.
    END
    Matched?
    N
    Y
    Stop?
    Interrupt is pending.
    N
    Y
     
    The I2C address match
    interrupt is generated.  
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-13  
    13.4 I/O Description 
    Signal I/O Description Pad Type 
    I2C0_SCL Input/Output I2C-bus interface0 Serial Clock Line Xi2c0SCL muxed 
    I2C0_SDA Input/Output I2C-bus interface0 Serial Data Line Xi2c0SDA muxed 
    I2C1_SCL Input/Output I2C-bus interface1 Serial Clock Line Xi2c1SCL muxed 
    I2C1_SDA Input/Output I2C-bus interface1 Serial Data Line Xi2c1SDA muxed 
    I2C2_SCL Input/Output I2C-bus interface2 Serial Clock Line XuRTSn_1 muxed 
    I2C2_SDA Input/Output I2C-bus interface2 Serial Data Line XuCTSn_1 muxed 
    I2C3_SCL Input/Output I2C-bus interface3 Serial Clock Line XuRTSn_2 muxed 
    I2C3_SDA Input/Output I2C-bus interface3 Serial Data Line XuCTSn_2 muxed 
    I2C4_SCL Input/Output I2C-bus interface4 Serial Clock Line XspiCSn_0 muxed 
    I2C4_SDA Input/Output I2C-bus interface4 Serial Data Line XspiCLK_0 muxed 
    I2C5_SCL Input/Output I2C-bus interface5 Serial Clock Line XspiMOSI_0 muxed 
    I2C5_SDA Input/Output I2C-bus interface5 Serial Data Line XspiMISO_0 muxed 
    I2C6_SCL Input/Output I2C-bus interface6 Serial Clock Line Xi2s2SDO muxed 
    I2C6_SDA Input/Output I2C-bus interface6 Serial Data Line Xi2s2SDI muxed 
    I2C7_SCL Input/Output I2C-bus interface7 Serial Clock Line XpwmTOUT_3 muxed 
    I2C7_SDA Input/Output I2C-bus interface7 Serial Data Line XpwmTOUT_2 muxed 
    I2C0_ISP_SCL Input/Output I2C-bus interface 0 Serial Clock Line for ISP XispI2C0SCL muxed 
    I2C0_ISP_SDA Input/Output I2C-bus interface 0 Serial Data Line for ISP XispI2C0SDA muxed 
    I2C1_ISP_SCL Input/Output I2C-bus interface 1 Serial Clock Line for ISP XispI2C1SCL muxed 
    I2C1_ISP_SDA Input/Output I2C-bus interface 1 Serial Data Line for ISP XispI2C1SDA muxed 
    NOTE: I2C-bus Interface for HDMI PHY and SATA PHY is internally connected 
     
     
     
      
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-14  
    13.5 Register Description 
    13.5.1 Register Map Summary 
     Base Address: 0x12C6_0000 (I2C0) 
     Base Address: 0x12C7_0000 (I2C1) 
     Base Address: 0x12C8_0000 (I2C2) 
     Base Address: 0x12C9_0000 (I2C3) 
     Base Address: 0x12CA_0000 (I2C4) 
     Base Address: 0x12CB_0000 (I2C5) 
     Base Address: 0x12CC_0000 (I2C6) 
     Base Address: 0x12CD_0000 (I2C7) 
     Base Address: 0x12CE_0000 (I2C_HDMI) 
     Base Address: 0x1313_0000 (I2C0_ISP) 
     Base Address: 0x1314_0000 (I2C1_ISP) 
     Base Address: 0x121D_0000 (I2C_SATAPHY) 
    Register Offset Description Reset Value 
    I2CCONn 0x0000 Specifies the I2C-bus interface0 control register  0x0X 
    I2CSTATn 0x0004 Specifies the I2C-bus interface0 control/status register  0x00 
    I2CADDn 0x0008 Specifies the I2C-bus interface0 address register  0xXX 
    I2CDSn 0x000C Specifies the I2C-bus interface0 transmit/receive data shift register  0xXX 
    I2CLCn 0x0010 Specifies the I2C-bus interface0 multi-master line control register 0x00 
     
     
      
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-15  
    13.5.1.1 I2CCONn (n = 0 to 7)  
     Base Address: 0x12C6_0000 (I2C0) 
     Base Address: 0x12C7_0000 (I2C1) 
     Base Address: 0x12C8_0000 (I2C2) 
     Base Address: 0x12C9_0000 (I2C3) 
     Base Address: 0x12CA_0000 (I2C4) 
     Base Address: 0x12CB_0000 (I2C5) 
     Base Address: 0x12CC_0000 (I2C6) 
     Base Address: 0x12CD_0000 (I2C7) 
     Base Address: 0x12CE_0000 (I2C_HDMI) 
     Base Address: 0x1313_0000 (I2C0_ISP) 
     Base Address: 0x1314_0000 (I2C1_ISP) 
     Base Address: 0x121D_0000 (I2C_SATAPHY) 
     Address = Base Address + 0x0000, Reset Value = 0x0X 
    Name Bit Type Description Reset Value 
    Acknowledge 
    generation (1) [7] RW 
    I2C-bus Acknowledge Enable bit 
    0 = Disables 
    1 = Enables 
    In Tx mode, the I2CSDA is free in the ACK time. 
    In Rx mode, the I2CSDA is L in the ACK time. 
    0 
    Tx clock source 
    selection [6] RW 
    Source Clock of I2C-bus Transmit Clock Prescaler 
    Selection bit 
    0 = I2CCLK = fPCLK/16  
    1 = I2CCLK = fPCLK/512 
    0 
    Tx/Rx Interrupt (5) [5] RW 
    I2C-Bus Tx/Rx Interrupt Enable/Disable bit 
    0 = Disables  
    1 = Enables 
    0 
    Interrupt pending flag 
    (2) (3)  [4] S 
    I2C-Bus Tx/Rx Interrupt Pending Flag  
    This bit cannot be written to 1. When this bit is 
    read as 1, the I2CSCL is tied to L and the I2C is 
    stopped. To resume the operation, clear this bit as 
    0. 
    0 = 1) No interrupt is pending (when Read)  
        2) Clear pending condition and 
               resume the operation (when Write). 
    1 = 1) Interrupt is pending (when Read) 
        2) N/A (when Write) 
    0 
    Transmit clock value 
    (4) [3:0] RW 
    I2C-bus Transmit Clock Prescaler 
    This 4-bit prescaler value determines the I2C-Bus 
    transmit clock frequency according to the following 
    formula: 
    Tx clock = I2CCLK/(I2CCON[3:0] + 1) 
    –= 
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-16  
    NOTE:  
    1 While interfacing with EEPROM, the ACK generation may be disabled before reading the last data to generate the STOP  
      condition in Rx mode. 
    2.  An I2C-Bus interrupt occurs when: 
     1) A 1-byte transmit or receive operation is complete. Alternatively, ACK period is finished. 
     2) A general call or a slave address match occurs. 
     3) Bus arbitration fails. 
    3. To adjust the setup time of SDA before SCL rising edge, I2CDS should be written before clearing the I2C interrupt  
          pending bit.  
    4. I2CCLK is determined by I2CCON[6]. 
       Tx clock can vary by SCL transition time. When I2CCON[6] = 0, I2CCON[3:0] = 0x0 or 0x1 is not available. 
    5. When the I2CCON[5] = 0, I2CCON[4] does not operate correctly.  
        Therefore, It is recommended to set I2CCON[5] = 1, even when you do not use the I2C interrupt. 
     
      
    						
    							Samsung Confidential  
    Exynos 5250_UM 13 IIC-Bus Interface 
     13-17  
    13.5.1.2 I2CSTATn (n = 0 to 7) 
     Base Address: 0x12C6_0000 (I2C0) 
     Base Address: 0x12C7_0000 (I2C1) 
     Base Address: 0x12C8_0000 (I2C2) 
     Base Address: 0x12C9_0000 (I2C3) 
     Base Address: 0x12CA_0000 (I2C4) 
     Base Address: 0x12CB_0000 (I2C5) 
     Base Address: 0x12CC_0000 (I2C6) 
     Base Address: 0x12CD_0000 (I2C7) 
     Base Address: 0x12CE_0000 (I2C_HDMI) 
     Base Address: 0x1313_0000 (I2C0_ISP) 
     Base Address: 0x1314_0000 (I2C1_ISP) 
     Base Address: 0x121D_0000 (I2C_SATAPHY) 
     Address = Base Address + 0x0004, Reset Value = 0x00 
    Name Bit Type Description Reset Value 
    Mode selection [7:6] RWX 
    I2C-Bus Master/Slave Tx/Rx Mode Select bits 
    00 = Slave Receive Mode 
    01 = Slave Transmit Mode 
    10 = Master Receive Mode 
    11 = Master Transmit Mode 
    00 
    Busy signal 
    status/START STOP 
    condition 
    [5] S 
    I2C-Bus Busy Signal Status bit 
    0 = (Read) Not busy (If Read) 
    (write) STOP signal generation 
    1 = (Read) Busy (If Read)  
    (write) START signal generation 
    The data in I2CDS is transferred  
    automatically after the start signal. 
    0 
    Serial output [4] S 
    I2C-Bus Data Output Enable/Disable bit 
    0 = Disables Rx/Tx 
    1 = Enables Rx/Tx 
    0 
    Arbitration status flag [3] R 
    I2C-Bus Arbitration Procedure Status Flag bit 
    0 = Bus arbitration successful 
    1 = Bus arbitration failed during serial I/O 
    0 
    Address-as-slave 
    status flag [2] R 
    I2C-Bus Address-as-slave Status Flag bit 
    0 = Cleared when START/STOP condition was 
    detected 
    1 = Received slave address matches the address 
    value in the I2CADD 
    0 
    Address zero status 
    flag [1] R 
    I2C-Bus Address Zero Status Flag bit 
    0 = Cleared when START/STOP condition is 
    detected  
    1 = Received slave address is 00000000b 
    0  
    						
    All Samsung manuals Comments (0)