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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-185  
5.9.1.188 BPLL_CON1 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0114, Reset Value = 0x0020_3800 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x0=
DCC_ENB=[21]=RW=
Enables Duty Cycle Corrector==
(only for monitoring)=
0 ==Enables DCC=
1 = Disables DCC=
0x1=
AFC_ENB=x20]=RW=
Decides=whether AFC is enabled or not (Active-low)=
0 ==Enables AFC=
1 = Disables AFC=
0x0=
FSEL=x19]=RW=
Monitoring=Frequency Select pin=
0 = FVCO_OUT ==FREF=
1 = FVCO_OUT = FVCl=
0x0=
RSVD=x18:17]=–=Reserved=0x0=
FEED_EN=[16]=RW=Enable pin for FEED_OUT (Active-high)=0x0=
LOCK_CON_OUT=[15:14]=RW=Lock detector setting of the=Output margin=0x0=
LOCK_CON_IN=[13:12]=RW=Lock detector setting of the=Input margin=0x3=
LOCK_CON_DLY=[11:8]=RW=Lock detector setting of the=detection resolution=0x8=
RSVD=[7:5]=–=Reserved=0x0=
EXTAFC=[4:0]=RW=Enable pin for FVCO_OUT (Active-high)=0x0=
=
AFC automatically selects adaptive frequency=curve of VCO using switched=current bank for:=
ο‚· Wide range  
ο‚· High phase noise (or Jitter)  
ο‚· Fast lock time 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on 
recommended AFC_ENB and EXTAFC values.
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Exynos 5250_UM 5 Clock Controller 
 5-186  
5.9.1.189 CLK_SRC_CDREX 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0200, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
MUX_MCLK=
_DPHY_SEi=[8]=RW=
Control MUX_MCLK_DPHY=
0 = SCLK_MPLi=
1 = SCLK_BPLi=
0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_MCLK=
_CDREX_SEL=[4]=RW=
Control MUX_MCLK_CDREX=
0 = SCLK_MPLi=
1 = SCLK_BPLi=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
MUX_BPLL_SEL=x0]=RW=
Control MUX_BPLL=
0 = XXTI=
1 = MOUT_BPLL_FOUT=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-187  
5.9.1.190 CLK_MUX_STAT_CDREX 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0400, Reset Value = 0x0011_1111 
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0x0=
SCLK_MPLL_SEi=x22:20]=o=
Selection signal=(SCLK_MPLL) status of 
MUX_MPLL=
001== XXTI=
010 = MPLL_FOUT_RGT=
1xx = On changing=
0x1=
RSVD=[19]=–=Reserved=0x0=
MPLL_FOUT_SEi=x18:16]=o=
Selection signal status of=MUX_MPLL_FOUT=
001 = MPLL_FOUT_800=
010 = MPLL_FOUT=
1xx = On changing=
0x1=
RSVD=[19]=–=Reserved=0x0=
BPLL_FOUT_SEi=[14:12]=o=
Selection signal status of=MUX_BPLL_FOUT=
001 = BPLL_FOUT_800=
010 = BPLL_FOUT=
1xx===On changing=
0x1=
RSVD=x11]=–=Reserved=0x0=
MCLK_DPHY=
_SEL=[10:8]=o=
Selection signal status of MUX_MCLK_DPHY=
001 = SCLK_MPLi=
010 = SCLK_BPLi=
1xx===On changing=
0x1=
RSVD=[7]=–=Reserved=0x0=
MCLK_CDREu=
_SEi=[6:4]=o=
Selection signal status of=MUX_MCLK_CDREX=
001 = SCLK_MPLi=
010 = SCLK_BPLi=
1xx===On changing=
0x1=
RSVD=[3]=–=Reserved=0x0=
BPLL_SEL=x2:0]=o=
Selection signal status of=MUX_BPLL=
001 = XXTI=
010 = MOUT_BPLL_FOUT=
1xx==On changing=
0x1=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-188  
5.9.1.191 CLK_DIV_CDREX 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
MCLK_CDREX2=
_RATIO=[30:28]=RW=
DIs_MCLK_CDREX2 clock divider=oatio=
MCLK_CDREX2== 
MOUT_MCLK_CDREX/(MCLK_CDREX2_RATIl=+=
1)=
0x0=
RSVD=[27]=–=Reserved=0x0=
ACLK_SFRTZASC
P_RATIl=[26:24]=RW=
DIs_ACLK_SFRTZASCP clock divider oatio=
ACLK_SFRTZASCP== 
ACLK_CDREX/(ACLK_SFRTZASCP_RATIl=+=1)=
0x0=
RSVD=[23]=–=Reserved=0x0=
MCLK_DPHY=
_RATIO=[22:20]=RW=
DIs_MCLK_DPHY=clock divider Ratio=
MCLK_DPHY== 
MOUT_MCLK_DPHY/(MCLK_DPHY_RATIO + 1)=
0x0=
RSVD=[19]=–=Reserved=0x0=
MCLK_CDREX=
_RATIO=[18:16]=RW=
DIs_MCLK_CDREu=clock divider Ratio=
MCLK_CDREX== 
MOUT_MCLK_CDREu/(MCLK_CDREX_RATIO=+=1)=
0x0=
RSVD=[15:7]=–=Reserved=0x0=
PCLK_CDREX=
_RATIO=[6:4]=RW=
DIs_PCLK_CDREu=clock divider Ratio=
PCLK_CDREX = 
MCLK_CDREX/(PCLK_CDREX_RATIO + 1)=
0x0=
RSVD=[3]=–=Reserved=0x0=
ACLK_CDREX=
_RATIO=[2:0]=RW=
DIs_ACLK_CDREu=clock divider Ratio=
ACLK_CDREX== 
MCLK_CDREX2/(ACLK_CDREX_RATIO + 1)=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-189  
5.9.1.192 CLK_DIV_STAT_CDREX 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:29] –=Reserved=0x0=
DIV_MCLK=
_CDREX2=[28]=o=
DIs_MCLK_CDREX2=status=
0== Stable=
1 = Divider is changing=
0x0=
RSVD=[27:25]=–=Reserved=0x0=
DIV_ACLK=
_SFRTZASCP=[24]=o=
DIs_ACLK_SFRTZASCP status=
0== Stable=
1 = Divider is changing=
0x0=
RSVD=[23:21]=–=Reserved=0x0=
DIV_MCLK=
_DPHY=[20]=o=
DIs_MCLK_DPHY=status=
0 = Stable=
1 = Divider is=changing=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
DIV_MCLK=
_CDREX=[16]=o=
DIs_MCLK_CDREu=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[15:5]=–=Reserved=0x0=
DIV_PCLK=
_CDREX=[4]=o=
DIs_PCLK_CDREu=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_ACLK=
_CDREX=[0]=o=
DIs_ACLK_CDREu=status=
0 = Stable=
1 ==Divider is changing=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-190  
5.9.1.193 CLK_GATE_IP_CDREX 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0900, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x3F=
CLK_TZASC=
_CBXt=[25]=RW=
Gating AXI=Clock for TZASC_XCBXW and DRAM 
controller port1=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_CBXo=[24]=RW=
Gating AXI=Clock for TZASC_XCBXR=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_DRBXW=[23]=RW=
Gating AXI=Clock for TZASC_XDRBXW and DRAM=
controller port3=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_DRBXR=[22]=RW=
Gating AXI=Clock for TZASC_XDRBXo=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_XLBXW=[21]=RW=
Gating AXI clock for TZASC_XLBXW=and DRAM=
controller port0=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_XLBXR=[20]=RW=
Gating AXI clock for=TZASC_XLBXo=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_XR1BXt=[19]=RW=
Gating AXI clock for TZASC_XR1BXt=and DRAM=
controller port2=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_XR1BXo=[18]=RW=
Gating AXI clock for TZASC_XR1BXo=
0== Masks=
1 = Passes=
0x1=
RSVD=[17:7]=–=Reserved=0x1FFF=
CLh=
_SFRTZASCP=[6]=RW=
Gating all=Clocks for AXI2APB_TZASCP and=
AXI_CNVSu=
0== Masks=
1 = Passes=
0x1=
CLK_DPHY1=[5]=RW=
Gating=DLL Clocks for LPDDRHPHY1=
0== Masks=
1 = Passes=
0x1=
CLK_DPHY0=[4]=RW=
Gating=DLL Clocks for LPDDRHPHY0=
0== Masks=
1 = Passes=
0x1=
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Exynos 5250_UM 5 Clock Controller 
 5-191  
Name Bit Type Description Reset Value 
CLK_DREX2 [3] RW 
Gating all Clocks for DRAM controller and clk2x for 
LPDDRHPHY0 and LPDDRHPHY1 
0 = Masks 
1 = Passes 
0x1 
CLK 
_SFRCDREXP [2] RW 
Gating all Clocks for AHB2APB_CDREXP and 
ASYNCAHBM_PCX_CDREXP 
0 = Masks 
1 = Passes 
0x1 
RSVD [1:0] – Reserved 0x3
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Exynos 5250_UM 5 Clock Controller 
 5-192  
5.9.1.194 DMC_FREQ_CTRL 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0914, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:15] –=Reserved=0x0=
MCLK_CDREX2=
_RATIO=[14:12]=RW=
DIV_MCLK_CDREX2 clock divider oatio=
MCLK_CDREX2 = MOUT_MCLK_DPHY/==
(MCLK_CDREX2_RATIO + 1)=
0x0=
RSVD=[11]=–=Reserved=0x0=
MCLK_DPHY=
_RATIO=[10:8]=RW=
DIV_MCLK_DPHY clock divider oatio=
MCLK_DPHY = MOUT_MCLK_DPHY/==
(MCLK_DPHY_RATIO + 1)=
0x0=
RSVD=[7:0]=–=Reserved=0x0=
=
5.9.1.195 DREX2_PAUSE 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x091C, Reset Value = 0xFFF8_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x7FFC7FFF=
ENABLE=x0]=ot=
Enable PAUSE function of DREXIf=
0 = Disables=
1 = Enables=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-193  
5.9.1.196 CLKOUT_CMU_CDREX 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = MCLK_CDREX=
00001 = ACLK_CDREX=
00010 = PCLK_CDREX=
00011== RCLK_CDREX=
0x0=
=
5.9.1.197 CLKOUT_CMU_CDREX_DIV_STAT 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIs_CLKOUT Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.198 LPDDR3PHY_CTRL 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0A10, Reset Value = 0x0000_0001 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
PHY_RESET=[0]=RW=RESET=for DDR3 memory=0x1=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-194  
5.9.1.199 LPDDR3PHY_CON3 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0A20, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
DRAM_POP_EN [31] RW Set this bit to 1 for POP 0x0 
RSVD [30:0] –=Reserved=0x0=
=
5.9.1.200 PLL_DIV2_SEL 
ο‚· Base Address: 0x1003_0000 
ο‚· Address = Base Address + 0x0A24, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
MPLL_FOUT_SEi=x4]=RW=
Control MUX_MPLL_FOUT=
0== MPLL_FOUT/2=
1== MPLL_FOUT=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
BPLL_FOUT_SEL=x0]=RW=
Control MUX_BPLL_FOUT=
0== BPLL_FOUT/2=
1== BPLL_FOUT=
0x0=
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