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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-257  
4.4.1.368 EXT_INT20_FIXPRI 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0B2C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:3] –=Reserved=0x00000000=
Highest_EINT=
_NUM=[2:0]=RW=Interrupt number of=the highest priority in External Interrupt=
Group 7 (EXT_INT20) when fixed priority mode: 0=to=7=0x0=
=
4.4.1.369 EXT_INT21_FIXPRI 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0B30, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:3] –=Reserved=0x00000000=
Highest_EINT=
_NUM=[2:0]=RW=Interrupt number of the highest priority in External Interrupt=
Group 8 (EXT_INT21) when fixed priority mode: 0=to=7=0x0=
=
4.4.1.370 EXT_INT22_FIXPRI 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0B34, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:3] –=Reserved=0x00000000=
Highest_EINT=
_NUM=[2:0]=RW=Interrupt number of the highest priority in External Interrupt=
Group 9 (EXT_INT22) when fixed priority mode: 0=to=7=0x0=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-258  
4.4.1.371 GPV0CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GPV0CON[7] [31:28] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[7] 
0x3 to 0xE = Reserved 
0xF = EXT_INT60[7] 
0x00 
GPV0CON[6] [27:24] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[6] 
0x3 to 0xE = Reserved 
0xF = EXT_INT60[6] 
0x00 
GPV0CON[5] [23:20] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[5] 
0x3 to 0xE = Reserved 
0xF = EXT_INT60[5] 
0x00 
GPV0CON[4] [19:16] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[4] 
0x3 to 0xE = Reserved 
0xF = EXT_INT60[4] 
0x00 
GPV0CON[3] [15:12] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[3] 
0x3 to 0xE = Reserved 
0xF = EXT_INT60[3] 
0x00 
GPV0CON[2] [11:8] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[2] 
0x3 to 0xE = Reserved 
0xF = EXT_INT60[2] 
0x00 
GPV0CON[1] [7:4] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[1] 
0x3 to 0xE = Reserved 
0xF = EXT_INT60[1] 
0x00 
GPV0CON[0] [3:0] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[0] 
0x3 to 0xE = Reserved 
0xF = EXT_INT60[0] 
0x00
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Exynos 5250_UM 4 Pad Control 
 4-259  
4.4.1.372 GPV0DAT 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0004, Reset Value = 0x00 
Name Bit Type Description Reset Value 
GPV0DAT[7:0] [7:0] RWX 
When you configure the port as input port, the 
corresponding bit is the pin state. When you configure 
the port as output port, the pin state is the same as the 
corresponding bit. W hen you configure the port as 
functional pin, the undefined value will be read. 
0x00 
 
4.4.1.373 GPV0PUD 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0008, Reset Value = 0x5555 
Name Bit Type Description Reset Value 
GPV0PUD[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x5555 
 
4.4.1.374 GPV0DRV 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x000C, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
GPV0DRV[n] 
[2n + 1:2n] 
n = 0 to 7 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 7 RW Reserved. Should be zero. 0x00_0000
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Exynos 5250_UM 4 Pad Control 
 4-260  
4.4.1.375 GPV0CONPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0010, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV0[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Output 0 
0x1 = Output 1 
0x2 = Input 
0x3 = Previous state 
0x00 
 
4.4.1.376 GPV0PUDPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0014, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV0[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up enabled 
0x00
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Exynos 5250_UM 4 Pad Control 
 4-261  
4.4.1.377 GPV1CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0020, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GPV1CON[7] [31:28] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[15] 
0x3 to 0xE = Reserved 
0xF = EXT_INT61[7] 
0x00 
GPV1CON[6] [27:24] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[14] 
0x3 to 0xE = Reserved 
0xF = EXT_INT61[6] 
0x00 
GPV1CON[5] [23:20] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[13] 
0x3 to 0xE = Reserved 
0xF = EXT_INT61[5] 
0x00 
GPV1CON[4] [19:16] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[12] 
0x3 to 0xE = Reserved 
0xF = EXT_INT61[4] 
0x00 
GPV1CON[3] [15:12] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[11] 
0x3 to 0xE = Reserved 
0xF = EXT_INT61[3] 
0x00 
GPV1CON[2] [11:8] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[10] 
0x3 to 0xE = Reserved 
0xF = EXT_INT61[2] 
0x00 
GPV1CON[1] [7:4] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[9] 
0x3 to 0xE = Reserved 
0xF = EXT_INT61[1] 
0x00 
GPV1CON[0] [3:0] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_RXD[8] 
0x3 to 0xE = Reserved 
0xF = EXT_INT61[0] 
0x00
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Exynos 5250_UM 4 Pad Control 
 4-262  
4.4.1.378 GPV1DAT 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0024, Reset Value = 0x00 
Name Bit Type Description Reset Value 
GPV1DAT[7:0] [7:0] RWX 
When you configure the port as input port, the 
corresponding bit is the pin state. When you configure 
the port as output port, the pin state is the same as the 
corresponding bit. W hen you configure the port as 
functional pin, the undefined value will be read. 
0x00 
 
4.4.1.379 GPV1PUD 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0028, Reset Value = 0x5555 
Name Bit Type Description Reset Value 
GPV1PUD[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x5555 
 
4.4.1.380 GPV1DRV 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x002C, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
GPV1DRV[n] 
[2n + 1:2n] 
n = 0 to 7 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 7 RW Reserved. Should be zero. 0x00_0000
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Exynos 5250_UM 4 Pad Control 
 4-263  
4.4.1.381 GPV1CONPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0030, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV1[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Output 0 
0x1 = Output 1 
0x2 = Input 
0x3 = Previous state 
0x00 
 
4.4.1.382 GPV1PUDPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0034, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV1[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x00
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Exynos 5250_UM 4 Pad Control 
 4-264  
4.4.1.383 ETC5PUD 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0048, Reset Value = 0x0005 
Name Bit Type Description Reset Value 
ETC5PUD[n] [2n + 1:2n] 
n = 0 to 1 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x0005 
 
ETC5PUD[1:0] controls Xc2cRXCLK[0]. 
ETC5PUD[3:2] controls Xc2cRXCLK[1]. 
 
4.4.1.384 ETC5DRV 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x004C, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
ETC5DRV[n] 
[2n + 1:2n] 
n = 0 to 1 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 1 RW Reserved. Should be zero. 0x00_0000 
 
ETC5DRV[1:0] controls Xc2cRXCLK[0]. 
ETC5DRV[3:2] controls Xc2cRXCLK[1].
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Exynos 5250_UM 4 Pad Control 
 4-265  
4.4.1.385 GPV2CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0060, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GPV2CON[7] [31:28] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[7] 
0x3 to 0xE = Reserved 
0xF = EXT_INT62[7] 
0x00 
GPV2CON[6] [27:24] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[6] 
0x3 to 0xE = Reserved 
0xF = EXT_INT62[6] 
0x00 
GPV2CON[5] [23:20] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[5] 
0x3 to 0xE = Reserved 
0xF = EXT_INT62[5] 
0x00 
GPV2CON[4] [19:16] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[4] 
0x3 to 0xE = Reserved 
0xF = EXT_INT62[4] 
0x00 
GPV2CON[3] [15:12] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[3] 
0x3 to 0xE = Reserved 
0xF = EXT_INT62[3] 
0x00 
GPV2CON[2] [11:8] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[2] 
0x3 to 0xE = Reserved 
0xF = EXT_INT62[2] 
0x00 
GPV2CON[1] [7:4] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[1] 
0x3 to 0xE = Reserved 
0xF = EXT_INT62[1] 
0x00 
GPV2CON[0] [3:0] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[0] 
0x3 to 0xE = Reserved 
0xF = EXT_INT62[0] 
0x00
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Exynos 5250_UM 4 Pad Control 
 4-266  
4.4.1.386 GPV2DAT 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0064, Reset Value = 0x00 
Name Bit Type Description Reset Value 
GPV2DAT[7:0] [7:0] RWX 
When you configure the port as input port, the 
corresponding bit is the pin state. When you configure 
the port as output port, the pin state is the same as the 
corresponding bit. W hen you configure the port as 
functional pin, the undefined value will be read. 
0x00 
 
4.4.1.387 GPV2PUD 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0068, Reset Value = 0x5555 
Name Bit Type Description Reset Value 
GPV2PUD[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x5555 
 
4.4.1.388 GPV2DRV 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x006C, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
GPV2DRV[n] 
[2n + 1:2n] 
n = 0 to 7 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 7 RW Reserved. Should be zero. 0x00_0000
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