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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-119  
15.5.5.3 VIDTCON0 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x0010, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
VBPDE [31:24] RW 
Vertical Back Porch  
Specifies the number of inactive lines at the start of a frame, 
after vertical synchronization period (only for even field of 
YVU interface) 
0x00 
VBPD [23:16] RW 
Vertical Back Porch  
Specifies the number of inactive lines at the start of a frame, 
after vertical synchronization period. 
0x00 
VFPD [15:8] RW 
Vertical Front Porch  
Specifies the number of inactive lines at the end of a frame, 
before vertical synchronization period. 
0x00 
VSPW [7:0] RW 
Vertical Sync Pulse Width  
Determines the high-level width of VSYNC pulse by counting 
the number of inactive lines. 
0x00 
 
15.5.5.4 VIDTCON1 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x0014, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
VFPDE [31:24] RW 
Vertical Front Porch  
Specifies the number of inactive lines at the end of a frame, 
before vertical synchronization period (only for the even field 
of YVU interface). 
0 
HBPD [23:16] RW 
Horizontal Back Porch  
Specifies the number of VCLK periods between the falling 
edge of HSYNC, and the start of active data. 
0x00 
HFPD  [15:8] RW 
Horizontal Front Porch  
Specifies the number of VCLK periods between the end of 
active data, and the rising edge of HSYNC. 
0x00 
HSPW [7:0] RW 
Horizontal Sync Pulse W idth  
Determines the high-level width of HSYNC pulse by counting 
the number of VCLK. 
0x00
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Exynos 5250_UM 15 Display Controller 
 15-120  
15.5.5.5 VIDTCON2 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x0018, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
LINEVAL_E [23] RW Determines the extended Vertical size of display. 0 
HOZVAL_E [22] RW Determines the extended Horizontal size of display. 0 
LINEVAL [21:11] RW Determines the Vertical size of display. 0 
HOZVAL [10:0] RW Determines the Horizontal size of display. 0 
NOTE: HOZVAL = (Horizontal display size) – 1 and LINEVAL = (Vertical display size) – 1. 
 
15.5.5.6 VIDTCON3 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x001C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
VSYNCEN [31] RW 
Enables VSYNC signal output. 
0 = Disables VSYNC signal output 
1 = Enables VSYNC signal output 
VBPD (VFPD, VSPW) + 1 < LINEVAL (when VSYNCEN = 1) 
0 
RSVD [30] –=Reserved (should be 0)=0=
FRMEN=[29]=RW=
Enables=the FRM signal output.=
0 = Disables=FRM signal output=
1 = Enables FRM signal output=
0=
INVFRM=[28]=RW=
Controls the polarity=of FRM=pulse.=
0 = Active=high= ==
1 = Active=low=
0=
FRMsRATE=[27:24]=RW=Controls=the FRM fssue=oate (maximum=rate up to 1:1S)=0x00=
oSVa=[23:16]=–=Reserved=0x00=
FRMVFPD=[15:8]=RW=Specifies the number of line between data active and FRM 
signal.=0x00=
FRMVSPW=[7:0]=RW=Specifies the=number of line of FRM=pignal tidth.=
(FRMVFPD + 1) + (FRMVSPW + 1) < LINEVAL + 1 (in RGB)=0x00=
=
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Exynos 5250_UM 15 Display Controller 
 15-121  
15.5.5.7 TRIGCON 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01A4, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:27] –=Reserved=0=
SWTRGCMD_=
W4BUc=[26]=t=
Specifies Window 4 double buffer trigger.=
1 = Enables software trigger=command=(Write-only)=
NOTE:=Only when TRGMODE_W4BUF is=set to=1=
0=
TRGMODE_=
W4BUc=[25]=RW=
Specifies Window 4 double buffer=trigger.=
0 = Disables=trigger=
1 = Enables=trigger=
0=
RSVD=[24:22]=–=Reserved=0=
SWTRGCMD_=
W3BUc=[21]=t=
Specifies=Window 3 double buffer trigger.=
1 = Enables=software trigger=command=(Write-only)=
NOTE:=Only when TRGMODE_W3BUF is=set to=1=
0=
TRGMODE_=
W3BUc=[20]=RW=
Specifies=Window 3 double buffer trigger.=
0 = Disables=trigger==
1 = Enables=trigger=
0=
RSVD=[19:17]=–=Reserved=0=
SWTRGCMD_=
W2BUc=[16]=t=
Specifies=Window 2 double buffer trigger.=
1 = Enables software trigger=command=(Write-only)=
NOTE:=Only when TRGMODE_W2BUF is=set to=1=
0=
TRGMODE_=
W2BUc=[15]=RW=
Specifies=Window 2 double buffer trigger.=
0 = Disables=trigger=
1 = Enables=trigger=
0=
RSVD=[14:12]=–=Reserved=0=
SWTRGCMD_=
W1BUc=[11]=t=
Specifies=Window 1 double buffer trigger.=
1 = Enables=software trigger=command=(Write-only)==
NOTE:=Only when TRGMODE_W1BUF is=set to=1=
0=
TRGMODE_=
W1BUc=[10]=RW=
Specifies=Window 1 double buffer trigger.=
0 = Disables=trigger=
1 = Enables=trigger=
0=
RSVD=[9:7]=–=Reserved=0=
SWTRGCMD_=
W0BUc=[6]=t=
Specifies=Window 0 double buffer trigger.=
1 ==Enables=software trigger=command=(Write-only)==
NOTE:=Only when TRGMODE_W0BUF is=set to=1=
0=
TRGMODE_=
W0BUc=[5]=RW=
Specifies=Window 0 double buffer trigger.=
0 = Disables=trigger=
1 = Enables=trigger=
0=
HWTRGMASK_f
80=[4]=RW=HW Triggering Mask=0=
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Exynos 5250_UM 15 Display Controller 
 15-122  
Name Bit Type Description Reset Value 
HWTRGEN_I80 [3] RW 
Enable I80 start trigger 
0 = Hardware Triggering Disable 
1 = Hardware Triggering Enable 
NOTE: Only when TRGMODE is 0 
0 
RSVD [2] - Reserved 0 
SWTRGCMD_I8
0_RGB [1] RW 
Enables I80 start trigger. 
1 = Software Triggering Command (write only) 
NOTE: Only when TRGMODE is 1 
0 
TRGMODE_I80 [0] RW 
Enables I80 start trigger. 
0 = Disables i80 Software Trigger 
1 = Enables i80 Software Trigger 
0 
NOTE: When two continuous software trigger inputs generate in some video clocks (VCLK), it is recognized as one.
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Exynos 5250_UM 15 Display Controller 
 15-123  
15.5.5.8 I80IFCONAn (n = 0 to 1) 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01B0, 0x01B4, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0=
LCD_CS_SETUP=[19:16]=RW=Specifies the=numbers of clock cycles for the active=
period of address signal=enable=to chip select=enable.=0=
LCD_WR=
_SETUP=[15:12]=RW=Specifies the=numbers of clock cycles for the active=
period of CS=signal=enable=to=write signal enable.=0=
LCD_WR_ACT=[11:8]=RW=Specifies the=numbers of clock cycles for the active=
period of chip select=enable.=0=
LCD_WR _HOLD=[7:4]=RW=Specifies the=numbers of clock cycles for the active=
period of chip select=disable to write signal disable.=0=
RSVD=[3]=–=Reserved==
RSPOi=[2]=RW=
Specifies the=polarity of RS Signal=
0 = Low  = ==
1 = High=
0=
RSVD=[1]=–=Reserved=0=
I80IFEN=[0]=RW=
Controls the=LCD I80 interface.=
0 = Disables=
1 = Enables=
0=
=
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Exynos 5250_UM 15 Display Controller 
 15-124  
15.5.5.9 I80IFCONBn (n = 0 to 1) 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01B8, 0x01BC, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:10] –=Reserved=0=
NORMAL_CMD_
ST=[9]=RW=
1 = Normal=Command Start=
NOTE:=Auto clears=after sending=out=one set of=
commands=
0=
RSVD=[8:7]=–=Reserved==
FRAME_SKIP=[6:5]=RW=
Specifies the I80 Interface Output Frame Decimation 
Factor.=
00 = 1 (No Skip)=
01 = 2=
10 = 3=
00=
RSVD=[4:0]=–=Reserved=0=
=
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Exynos 5250_UM 15 Display Controller 
 15-125  
15.5.5.10 LDI_CMDCON0 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01D0, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved==
CMD11_EN=[23:22]=RW=
00 = Disables=
01 = Enables Normal Command=
10 ==Reserved=
11 ==Reserved=
00=
CMD10_EN=[21:20]=RW=
00 = Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD9_EN=[19:18]=RW=
00 = Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD8_EN=[17:16]=RW=
00 ==Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD7_EN=[15:14]=RW=
00 = Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD6_EN=[13:12]=RW=
00 = Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD5_EN=[11:10]=RW=
00 = Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD4_EN=[9:8]=RW=
00 = Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD3_EN=[7:6]=RW=
00 = Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD2_EN=[5:4]=RW=
00 = Disables=
01 = Enables Normal Command=
10 = Reserved=
11 = Reserved=
00=
CMD1_EN=[3:2]=RW=00 = Disables=00=
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Exynos 5250_UM 15 Display Controller 
 15-126  
Name Bit Type Description Reset Value 
01 = Enables Normal Command 
10 = Reserved 
11 = Reserved 
CMD0_EN [1:0] RW 
00 = Disables 
01 = Enables Normal Command 
10 = Reserved 
11 = Reserved 
00
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Exynos 5250_UM 15 Display Controller 
 15-127  
15.5.5.11 LDI_CMDCON1 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01D4, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:10] –=Reserved=0=
CMD11_RS=[11]=RW=Controls=Command 11 Rp=0=
CMD10_RS=[10]=RW=Controls=Command 10 Rp=0=
CMD9_Rp=[9]=RW=Controls=Command 9 RS=0=
CMD8_Rp=[8]=RW=Controls=Command 8 RS=0=
CMD7_Rp=[7]=RW=Controls=Command 7 RS=0=
CMD6_Rp=[6]=RW=Controls=Command 6 RS=0=
CMD5_Rp=[5]=RW=Controls=Command 5 RS=0=
CMD4_Rp=[4]=RW=Controls=Command 4 RS=0=
CMD3_Rp=[3]=RW=Controls=Command 3 RS=0=
CMD2_Rp=[2]=RW=Controls=Command 2 RS=0=
CMD1_Rp=[1]=RW=Controls=Command 1 RS=0=
CMD0_Rp=[0]=RW=Controls=Command 0 RS=0=
=
=
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Exynos 5250_UM 15 Display Controller 
 15-128  
15.5.5.12 SIFCCON0 
 Base Address: 0x1442_0000 
 Address = Base Address + 0x01E0, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved (should be 0)=0=
SYS_ST_CON=[6]=RW=
Controls=LCD i80 System Interface ST Signal.=
0 = Low=
1 = High=
0=
SYS_RS_CON=[5]=RW=
Controls=LCD i80 System Interface RS Signal.=
0 = Low=
1 = High=
0=
SYS_nCS0_CON=[4]=RW=
Controls=LCD i80 System Interface nCS0 (main) Signal.=
0 = Disables (High)=
1 = Enables (Low)=
0=
SYS_nCS1_CON=[3]=RW=
Controls=LCD i80 System Interface nCS1 (sub) Signal.=
0 = Disables (High)=
1 = Enables (Low)=
0=
SYS_nOE_CON=[2]=RW=
Controls=LCD i80 System Interface=nOE Signal.=
0 = Disables (High)=
1 = Enables (Low)=
0=
SYS_nW E_CON=[1]=RW=
Controls=LCD i80 System Interface=nt E Signal.=
0 = Disables (High)=
1 = Enables (Low)=
0=
SCOMEN=[0]=RW=
Enables=LCD i80 System Interface Command Mode.=
0 = Disables (Normal Mode)=
1= Enables (Manual Command Mode)=
0=
=
=
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