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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-18  
Name Bit Type Description Reset Value 
Last-received bit 
status flag [0] R 
I2C-Bus Last-received Bit Status Flag bit 
0 = Last-received bit is 0 (ACK was received) 
1 = Last-received bit is 1 (ACK was not received) 
0
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-19  
13.5.1.3 I2CADDn (n = 0 to 7)  
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address: 0x1314_0000 (I2C1_ISP) 
 Base Address: 0x121D_0000 (I2C_SATAPHY) 
 Address = Base Address + 0x0008, Reset Value = 0xXX 
Name Bit Type Description Reset Value 
Slave address [7:0] RWX 
7-bit slave address, latched from the I2C-bus 
When serial output enable = 0 in the I2CSTAT, 
I2CADD is Write-enabled. The I2CADD value is 
read any time, regardless of the current serial output 
enable bit (I2CSTAT) setting. 
Slave address: [7:1] 
Not mapped: [0] 
–=
=
=
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-20  
13.5.1.4 I2CDSn (n = 0 to 7)  
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address: 0x1314_0000 (I2C1_ISP) 
 Base Address: 0x121D_0000 (I2C_SATAPHY) 
 Address = Base Address + 0x000C, Reset Value = 0xXX 
Name Bit Type Description Reset Value 
Data shift  [7:0] RWX 
8-bit data shift register for I2C-bus Tx/Rx operation 
When serial output enable = 1 in the I2CSTAT, 
I2CDS is Write-enabled. The I2CDS value is Read 
any time, regardless of the current serial output 
enable bit (I2CSTAT) setting. 
–=
=
=
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-21  
13.5.1.5 I2CLCn (n = 0 to 7)  
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address: 0x1314_0000 (I2C1_ISP) 
 Base Address: 0x121D_0000 (I2C_SATAPHY) 
 Address = Base Address + 0x0010, Reset Value = 0x00 
Name Bit Type Description Reset Value 
Filter enable [2] RW 
I2C-Bus Filter Enable bit  
When SDA port is operating as input, this bit should 
be High. This filter prevents error caused due to the 
glitch between two PCLK clock. 
0 = Disables Filter  
1 = Enables Filter  
0 
SDA output delay [1:0] RW 
I2C-Bus SDA Line Delay Length Selection bitsSDA 
line is delayed with the following clock time (PCLK) 
00 = 0 clocks        
01 = 5 clocks 
10 = 10 clocks          
11 = 15 clocks 
00
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-1  
14 Serial Peripheral Interface 
14.1 Overview 
Serial Peripheral Interface (SPI) in Exynos 5250 transfers serial data by using various peripherals. 
SPI includes two 8, 16, 32-bit shift registers to transmit and receive data. It transfers (shifts out serially) and 
receives (shifts in serially) data simultaneously. It supports the protocols for National Semiconductor Microwire 
and Motorola Serial Peripheral Interface.  
 
14.2 Features 
Features of SPI are: 
 Supports full duplex 
 Supports 8/16/32-bit shift register for Tx/Rx 
 Supports 8-bit/16-bit/32-bit bus interface 
 Supports the Motorola SPI protocol and National Semiconductor Microwire 
 Supports two independent 32-bit wide transmit and receive FIFOs:  
 Depth 64 in SPI port 0 and depth 16 in SPI port 1 and 2 
 Depth 64 in ISP-SPI port 0 and 1 
 Supports Master-mode and Slave-mode 
 Supports Receive-without-transmit operation 
 Supports Tx/Rx maximum frequency at up to 50 MHz
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-2  
14.2.1 Operation of Serial Peripheral Interface 
SPI transfers 1-bit serial data between Exynos 5250 and external device. SPI in Exynos 5250 supports CPU or 
DMA to transmit or receive FIFOs separately. It also supports to transfer data in both directions simultaneously. 
SPI has two channels: Tx channel and Rx channel. The Tx channel has the path from Tx FIFO to external device. 
The Rx channel has the path from external device to Rx FIFO. 
CPU or DMA must write data on the register SPI_TX_DATA, to write data in FIFO. Data on the register are 
automatically moved to Tx FIFOs. To read data from Rx FIFOs, CPU or DMA must access the SPI_RX_DATA 
register and data are automatically sent to the SPI_RX_DATA register. 
CMU registers controls the SPI operating frequency. Refer to Chapter 7 Clock Controller for more information. 
 
14.2.1.1 Operation Mode 
SPI has two modes:  
 Master mode 
 Slave mode 
In master mode, SPICLK is generated and transmitted to external device. The signal to select the slave, XspiCS#, 
indicates that the data is valid when XspiCS# is set to low level. XspiCS# must be set low level before packets are 
transmitted or received. 
 
14.2.1.2 FIFO Access 
SPI supports CPU and DMA access to FIFOs. Data size of CPU access and DMA access to FIFOs is selected 
either from 8-bit, 16-bit, or 32-bit data. When 8-bit data size is selected, valid bits are from 0-bit to 7-bit. User can 
define the trigger threshold to raise interrupt to CPU. The trigger level of each FIFO in port 0 is set by 4 bytes step 
from 0 byte to 252 bytes. Each FIFO in port 1 is set by 1 byte step from 0 byte to 63 bytes. TxDMAOn or 
RxDMAOn bit of SPI_MODE_CFG register must be set to use DMA access. DMA access supports only single 
transfer and 4-burst transfer. In Tx FIFO, DMA request signal is high until Tx FIFO is full. In Rx FIFO, DMA 
request signal is high when Rx FIFO is not empty. 
 
14.2.1.3 Trailing Bytes in the Rx FIFO 
Trailing bytes are the remaining bytes when the number of samples in Rx FIFO is less than the threshold value in 
INT or DMA 4 burst mode and when no additional data is received. To remove these bytes in Rx FIFO, It uses 
internal timer and interrupt signal. The value of internal timer is set to 1024 clocks based on APB BUS clock. 
When timer value is set to zero, interrupt signal occurs and CPU can eliminate trailing bytes in FIFO.
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-3  
14.2.1.4 Packet Number Control 
SPI controls the number of packets to be received in master mode. Set SFR (PACKET_CNT_REG) to receive any 
number of packets. SPI stops generating SPICLK when the number of packets is the same as 
PACKET_CNT_REG. The size of one packet depends on channel width.  
NOTE: One packet is 1 byte if channel width is configured as byte, and one packet is 4 bytes if channel width is configured as 
word. Mandatorily follow software or hardware reset before this function is reloaded.  
 
Software reset clears all registers except special function registers. However, hardware reset clears all registers. 
 
14.2.1.5 Chip Select Control 
Chip select XspiCS# is active in low signal. Alternatively, a chip is selected when XspiCS# input is 0. 
You can control XspiCS# automatically or manually.  
When you use manual control mode, AUTO_N_MANUAL must be cleared (Default value is 0). NSSOUT bit 
controls the XspiCS# level.  
When you use auto control mode, AUTO_N_MANUAL must be set to 1. XspiCS toggles between packets 
automatically. NCS_TIME_COUNT controls inactive period of XspiCS. NSSOUT is not available at this time. 
 
14.2.1.6 High Speed Operation as Slave 
Exynos 5250 SPI supports Tx/Rx operations up to 50 MHz. However, there is a limitation. When Exynos 5250 SPI 
works as a slave, there is a delay of more than 15 ns in worst operating condition. Such a large delay can cause 
setup violation at the SPI master device. To resolve this problem, Exynos 5250 SPI provides fast slave Tx mode 
by setting 1 to HIGH_SPEED bit of CH_CFG register. In this mode, MISO output delay is reduced by half cycle so 
that the SPI master device has more setup margin. 
However, the fast slave Tx mode can be used only when CPHA = 0.
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-4  
14.2.1.7 Feed Back Clock Selection 
Under SPI protocol spec, SPI master should capture the input data launched by slave (MISO) with its internal 
SPICLK.  
When SPI runs at high operating frequency such as 50 MHz, it is difficult to capture the MISO input because the 
required arrival time of MISO, which is an half cycle period in Exynos 5250, is shorter than the arrival time of 
MISO that consists of SPICLK output delay of SPI master, MISO output delay of SPI slave, and MISO input delay 
of SPI master. To resolve this problem, Exynos 5250 SPI provides three feedback clocks that are phase-delayed 
clock of internal SPICLK.  
A selection of feedback clock depends on MISO output delay of SPI slave. To capture MISO data correctly, it 
selects the feedback clock that satisfies this constraint: 
tSPIMIS (s) < tperiod/2-tSPISOD 
* tSPIMIS (s): MISO input setup time of SPI master on a given feedback clock selection s 
* tSPISOD: MISO output delay of SPI slave 
* tperiod: SPICLK cycle period 
 
When multiple feedback clocks meet the constraint, it selects the feedback clock with smallest phase delay. It is 
because a feedback clock with large phase delay may capture data of next cycle. 
For example, Exynos 5250 SPI CH1 with master configuration of 50 MHz operating frequency with1.8 V external 
voltage and 15 pF load, 270 degree phase-delayed feedback clock should be used when the MISO output delay 
of SPI slave is assumed as 11 ns (tSPIMIS (s) < 10 ns – 11 ns = – 1 ns). 
When the operating clock frequency is 33 MHz and other conditions are the same as the previous example, then it 
is better to use 180 degree phase-delayed feedback clock (tSPIMIS (s) < 15 ns – 11 ns = 4 ns).
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-5  
14.2.1.8 SPI Transfer Format 
Exynos 5250 supports four different formats for data transfer. Figure 14-1 illustrates four waveforms for SPICLK.  
 
    Figure 14-1   SPI Transfer Format  Cycle
MOSI
12345678
MSB654321LSB
654321LSB
SPICLK
MISOMSB
CPOL = 1, CPHA = 1 (Format B)
Cycle
MOSI
12345678
MSB654321LSB
654321LSB*MSB
SPICLK
MISOMSB
CPOL = 1, CPHA = 0 (Format A)
Cycle
MOSI
12345678
654321LSB
654321LSB
SPICLK
MISOLSB*
CPOL = 0, CPHA = 1 (Format B)
Cycle
MOSI
12345678
MSB654321LSB
654321LSB*MSB
SPICLK
MISOMSB
CPOL = 0, CPHA = 0 (Format A)
LSB*
MSB
MSB
*MSB : MSB of previous frame
LSB* : LSB of next frame
LSB* : LSB of next frame
*MSB : MSB of previous frame
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Exynos 5250_UM 14 Serial Peripheral Interface 
 14-6  
14.3 SPI Input Clock Description 
Figure 14-2 illustrates input clock diagram for SPI. 
 
    Figure 14-2   Input Clock Diagram for SPI 
Exynos 5250 provides SPI with a variety of clocks. As illustrated in the Figure 14-2, SPI uses SCLK_SPI clock, 
which is from clock controller. You can also select SCLK_SPI from various clock sources. Refer to Chapter 7 
Clock Controller to select SCLK_SPI. 
NOTE: SPI has an internal 2x clock divider. SCLK_SPI should be configured to have a double of the SPI operating clock 
frequency. 
 
 
 System Controller
DIVSPI0~2(1~16)
MUXSPI0~2
MOUTSPI0~2
XXTIXusbXTISCLK_HDMI27MSCLK_USBPHY0SCLK_USBPHY1SCLK_HDMIPHYSCLKMPLLSCLKEPLLSCLKVPLL
SPI_CLKDIV(2)
SPI
SCLK_SPI
( Max 100MHz )( Max 50MHz )
DIVSPI0~2_PRE(1~256)
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