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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-17  
Name Bit  Type Description Reset Value 
inverter on/off 1 = TOUT_0 Inverter-On 
Timer 0 manual 
update [1] RW 0 = No Operation    
1 = Updates TCNTB0,TCMPB0 0x0 
Timer 0 start/stop [0] RW 0 = Stops     
1 = Starts Timer 0 0x0
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-18  
10.5.1.4 TCNTB0  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x000C, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 0 count 
buffer [31:0] RW Timer 0 Count Buffer register 0x0000_0000 
 
10.5.1.5 TCMPB0 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0010, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 0 compare 
buffer [31:0] RW Timer 0 Compare Buffer register 0x0000_0000 
 
10.5.1.6 TCNTO0 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0014, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 0 count 
observation [31:0] R Timer 0 Count Observation register 0x0000_0000
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-19  
10.5.1.7 TCNTB1  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0018, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 1 count 
buffer [31:0] RW Timer 1 Count Buffer register 0x0000_0000 
 
10.5.1.8 TCMPB1 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x001C, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 1 compare 
buffer [31:0] RW Timer 1 Compare Buffer register 0x0000_0000 
 
10.5.1.9 TCNTO1 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0020, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 1 count 
observation [31:0] R Timer 1 Count Observation register 0x0000_0000
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-20  
10.5.1.10 TCNTB2 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0024, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 2 count 
buffer [31:0] RW Timer 2 Count Buffer register 0x0000_0000 
 
10.5.1.11 TCMPB2 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0028, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 2 compare 
buffer [31:0] RW Timer 2 Compare Buffer register 0x0000_0000 
 
10.5.1.12 TCNTO2 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x002C, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 2 count 
observation [31:0] R Timer 2 Count Observation register 0x0000_0000
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-21  
10.5.1.13 TCNTB3  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0030, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 3 count 
buffer [31:0] RW Timer 3 Count Buffer register 0x0000_0000 
 
10.5.1.14 TCMPB3 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0034, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 3 compare 
buffer [31:0] RW Timer 3 Compare Buffer register 0x0000_0000 
 
10.5.1.15 TCNTO3  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0038, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 3 count 
observation [31:0] R Timer 3 Count Observation register 0x0000_0000
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-22  
10.5.1.16 TCNTB4  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x003C, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 4 count 
buffer [31:0] RW Timer 4 Count Buffer register 0x0000_0000 
 
10.5.1.17 TCNTO4 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0040, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
Timer 4 count 
observation [31:0] R Timer 4 Count Observation register 0x0000_0000
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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-23  
10.5.1.18 TINT_CSTAT  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0044, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
RSVD [31:10] –=Reserved Bits=0x00000=
Timer 4 
interrupt status=[9]=p=Timer 4 Interrupt Status=bit==
Clears by writing 1 on this bit.=0x0=
Timer 3 
interrupt status=[8]=p=Timer 3 Interrupt Status=bit==
Clears by writing 1 on this bit.=0x0=
Timer 2 
interrupt status=[7]=p=Timer 2 Interrupt Status=bit==
Clears by writing 1 on this bit.=0x0=
Timer 1 
interrupt status=[6]=p=Timer 1 Interrupt Status=bit==
Clears=by writing 1 on this bit.=0x0=
Timer 0 
interrupt status=[5]=p=Timer 0 Interrupt Status=bit==
Clears by writing 1 on this bit.=0x0=
Timer 4 
interrupt enable=[4] =RW=
Enables Timer 4 Interrupt=
0 = Disables interrupt=
1 = Enables=interrupt=
0x0=
Timer 3 
interrupt enable=[3] =RW=
Enables Timer 3 Interrupt=
0 = Disables interrupt=
1 = Enables=interrupt=
0x0=
Timer 2 
interrupt enable=[2] =RW=
Enables Timer=2 Interrupt=
0 = Disables interrupt=
1 = Enables=interrupt=
0x0=
Timer 1 
interrupt enable=[1] =RW=
Enables Timer 1 Interrupt=
0 = Disables interrupt=
1 = Enables=interrupt=
0x0=
Timer 0 
interrupt enable=[0] =RW=
Enables Timer 0 Interrupt=
0 = Disables interrupt=
1 = Enables=interrupt=
0x0=
=
=
=
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Exynos 5250_UM 11 Watchdog Timer 
 11-1  
11 Watchdog Timer 
11.1 Overview 
Watchdog Timer (WDT) in Exynos 5250 is a timing device. You can use this device to resume the controller 
operation after malfunctioning due to noise and system errors. You can use WDT as a normal 16-bit interval timer 
to request interrupt service. WDT generates the reset signal. 
Both of WDT and PWM timer are normal generate internal interrupts for the ARM subsystem. The difference 
between WDT and PWM timer is that only WDT generates the reset signal. (Refer to PWM Timer chapter for more 
information on PWM Timer.) 
 
 
11.2 Features 
The features of WDT are: 
 Supports normal interval timer mode with interrupt request. 
 Activates internal reset signal if the timer count value reaches 0 (time-out).  
 Supports level-triggered interrupt mechanism
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Exynos 5250_UM 11 Watchdog Timer 
 11-2  
11.3 Functional Description 
This section includes: 
 WDT Operation 
 WTDAT and WTCNT 
 WDT Start 
 Consideration of debugging environment 
  
11.3.1 WDT Operation 
WDT timer uses PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding WDT 
clock and it divides the resulting frequency again.  
Figure 11-1 illustrates the functional block diagram of the WDT. 
 
    Figure 11-1   Watchdog Timer Block Diagram  
The Watchdog Timer Control (WTCON) specifies the prescaler value and frequency division factor. The valid 
prescaler values range from 0 to 28-1. You can select the frequency division factor as: 16, 32, 64, or 128. 
Use this equation to calculate W DT clock frequency and the duration of each timer clock cycle: 
t_watchdog = 1/(PCLK/(Prescaler value + 1)/Division_factor) 
  Res et  Signal Generat orW TC NT
(Down  Counter)PCLK
W TC ON[4: 3]
W TD AT
RESET
1/16
1/32
1/64
1/128
8-bit  Pres c aler
W TC ON[15: 8]W TC ON[2]W TC ON[0]
I nt errupt
MUX
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Exynos 5250_UM 11 Watchdog Timer 
 11-3  
11.3.2 WTDAT and WTCNT 
After you enable the WDT, you cannot reload the value of the Watchdog Timer Data (WTDAT) register 
automatically into the Watchdog Timer Counter (WTCNT) register. Therefore, you must write an initial value to the 
WTCN register before WDT starts. . 
 
11.3.3 WDT Start 
To start WDT, set WTCON[0] and WTCON[5] as 1. 
 
11.3.4 Consideration of Debugging Environment 
WDT must not operate when the Exynos 5250 is in debug mode that uses Embedded ICE.  
WDT determines if Exynos 5250 is currently in the debug mode from the CPU core signal (DBGACK signal). After 
the DBGACK signal is asserted, it does not activate the reset output of WDT as WDT expires.
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