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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-145  
    5.9.1.129 CLKDIV2_RATIO0 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0590, Reset Value = 0x0011_0110 
    Name Bit Type Description Reset Value 
    RSVD [31:21] –=Reserved=0x0=
    JPGX_DIV=[20]=RW=
    PCLK=divider ratio in JPGX_DIV (GEN_BLK)=
    PCLK_83_of_JPGX_DIV = ACLK_166/(JPGX_DIV 
    + 1)=
    0x1=
    RSVD=[19:18]=–=Reserved=0x0=
    DISP1_BLh=[17:16]=RW=
    PCLK divider ratio in DISP1_BLh=
    PCLK_100_of_DISP1_BLK = 
    ACLK_200_DISP1/(DISP1_BLK + 1)=
    then DISP1_BLK power goes off/on, this field 
    should be set to different value and be restored to 
    target value before DISP1_BLK power goes on.=
    0x1=
    RSVD=[15:9]=–=Reserved=0x0=
    GEN_BLK=[8]=RW=
    PCLK divider ratio in GEN_BLh=
    PCLK_133_of_GEN_BLh== ACLK_266/(GEN_BLK 
    + 1)=
    0x1=
    RSVD=[7:6]=–=Reserved=0x0=
    GSCL_BLK=[5:4]=RW=
    PCLK divider ratio in GSCL_BLK=
    PCLK_133_of_GSCLL_BLK = 
    ACLK_266_GSCL/(GSCL_BLK + 1)=
    then GSCL_BLK power goes off/on, this field=
    should be set to different value and be restored to 
    target value before GSCLK_BLK power goes on.=
    0x1=
    RSVD=[3:0]=–=Reserved=0x0=
    =
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-146  
    5.9.1.130 CLKDIV2_RATIO1 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0594, Reset Value = 0x0000_0105 
    Name Bit Type Description Reset Value 
    RSVD [31:10] –=Reserved=0x0=
    G3a_BLK_PCLh=x9:8]=RW=
    PCLK divider ratio in G3a_BLK=
    PCLK_of_G3a_BLK ==
    ACLK_400_G3a/(G3D_BLK_PCLK=+ 1)=
    0x1=
    RSVD=x7:4]=–=Reserved=0x0=
    FSYS_PCLKDBG=x3:2]=RW=
    PCLKDBG divider ratio in FSYS_BLh=
    PCLKDBG_of_FSYS_BLK = 
    ATCLK_of_FSYS_BLK/(FSYS_PCLKDBG + 1)=
    0x1=
    FSYS_ATCLK=x1:0]=RW=
    ATCLK divider ratio in FSYS_BLh=
    ATCLK_of_FSYS_BLK = 
    ACLK_400_IOP/(FSYS_ATCLK + 1)=
    0x1=
    =
    5.9.1.131 CLKDIV4_RATIO 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x05A0, Reset Value = 0x0000_0003 
    Name Bit Type Description Reset Value 
    RSVD [31:2] –=Reserved=0x0=
    MFC_BLh=[1:0]=RW=
    PCLK divider ratio in MFC_BLh=
    PCLK_83_of_MFC_BLK = ACLK_333/(MFC_BLK=
    + 1)=
    When MFC power goes off/on, this field should be=
    set to different value and be restored to target=
    value before MFC power goes on.=
    0x3=
    =
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-147  
    5.9.1.132 CLK_DIV_STAT_TOP0 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0610, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:25] –=Reserved=0x0=
    DIV_ACLK_400_G
    3D=x24]=o=
    DIs_ACLK_400_G3a=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=x23:21]=–=Reserved=0x0=
    DIV_ACLK_333=x20]=o=
    DIV_ACLK_333 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    DIV_ACLK_300=
    _GSCi=[19]=o=
    DIV_ACLK_300_GSCL status=
    0== Stable=
    1 = Divider is changing=
    0x0=
    DIV_ACLK_300=
    _DISP1=[18]=o=
    DIV_ACLK_300_DISP1 status=
    0== Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[17]=–=Reserved=0x0=
    DIV_ACLK_266=[16]=o=
    DIV_ACLK_266=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[15:13]=–=Reserved=0x0=
    DIV_ACLK_200=[12]=o=
    DIV_ACLK_200=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[11:9]=–=Reserved=0x0=
    DIV_ACLK_1SS=[8]=o=
    DIV_ACLK_1SS=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[7:1]=–=Reserved=0x0=
    DIV_ACLK_66=[0]=o=
    DIV_ACLK_66=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-148  
    5.9.1.133 CLK_DIV_STAT_TOP1 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0614, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:29] –=Reserved=0x0=
    DIV_ACLK_MIPf=
    _HSI_TXBASb=x28]=o=
    DIs_ACLK_MIPI_HSI_TXBASb=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=x27:25]=–=Reserved=0x0=
    DIV_ACLK_6S=
    _PRE=x24]=o=
    DIV_ACLK_66_PRb=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=x23:21]=–=Reserved=0x0=
    DIV_ACLK_400=
    _ISP=x20]=o=
    DIV_ACLK_400_ISm=status=
    0 = Stable=
    1 ==Divider is changing=
    0x0=
    RSVD=x19:17]=–=Reserved=0x0=
    DIV_ACLK_400=
    _IOP=[16]=o=
    DIV_ACLK_400_IOP=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[15:0]=–=Reserved=0x0=
    =
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-149  
    5.9.1.134 CLK_DIV_STAT_GSCL 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0620, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:29] –=Reserved=0x0=
    DIV_GSCL=
    _WRAP_B=[28]=o=
    DIV_GSCL_WRAP_B=status=
    0 = Stable=
    1== Divider is changing=
    0x0=
    RSVD=[27:25]=–=Reserved=0x0=
    DIV_GSCL=
    _WRAP_A=[24]=o=
    DIV_GSCL_WRAP_A=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=x23:21]=–=Reserved=0x0=
    RSVD=[20]=–=Reserved=0x0=
    RSVD=[19:17]=–=Reserved=0x0=
    DIV_CAM0=[16]=o=
    DIV_CAM0=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[15:13]=–=Reserved=0x0=
    DIV_CAM=
    _BAYER=[12]=o=
    DIV_CAM_BAYER=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[11:0]=–=Reserved=0x0=
    =
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-150  
    5.9.1.135 CLK_DIV_STAT_DISP1_0 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x062C, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:26] –=Reserved=0x0=
    DIV_HDMI_PIXEL=[25]=o=
    DIV_HDMI_PIXEL=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    DIV_DP1_EXT=
    _MST_VID=x24]=o=
    DIV_DP1_EXT_MST_VIa=status=
    0 = Stable=
    1 ==Divider is changing=
    0x0=
    RSVD=x23:21]=–=Reserved=0x0=
    DIV_MIPI1_PRE=[20]=o=
    DIV_MIPI1_PRE status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[19:17]=–=Reserved=0x0=
    DIV_MIPI1=[16]=o=
    DIV_MIPI1=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[15:1]=–=Reserved=0x0=
    DIV_FIMD1=[0]=o=
    DIV_FIMD1=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    =
    =
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-151  
    5.9.1.136 CLK_DIV_STAT_GEN 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x063C, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:5] –=Reserved=0x0=
    DIV_JPEG=[4]=o=
    DIV_JPEG=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[3:1]=–=Reserved=0x0=
    =
    5.9.1.137 CLK_DIV_STAT_MAU 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0644, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:5] –=Reserved=0x0=
    DIV_PCM0=[4]=o=
    DIV_PCM0 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[3:1]=–=Reserved=0x0=
    DIV_AUDIO0=[0]=o=
    DIV_AUDIO0 status=
    0 = Stable=
    1 = Divider is=changing=
    0x0=
    =
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-152  
    5.9.1.138 CLK_DIV_STAT_FSYS0 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0648, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:21] –=Reserved=0x0=
    DIV_USBDRD30=[24]=o=
    DIV_USBDRD30=status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=x23:21]=–=Reserved=0x0=
    DIV_SATA=[20]=o=
    DIV_SATA=status=
    0 ==Stable=
    1 = Divider is changing=
    –=
    RSVD=[19:0]=–=Reserved=0x0=
    =
    5.9.1.139 CLK_DIV_STAT_FSYS1 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x064C, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:25] –=Reserved=0x0=
    DIV_MMC1_PRE=[24]=o=
    DIV_MMC1_PRE status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[23:17]=–=Reserved=0x0=
    DIV_MMC1=[16]=o=
    DIV_MMC1 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[15:9]=–=Reserved=0x0=
    DIV_MMC0_PRE=[8]=o=
    DIV_MMC0_PRE status=
    0 = Stable=
    1 = Divider is=changing=
    0x0=
    RSVD=[7:1]=–=Reserved=0x0=
    DIV_MMC0=[0]=o=
    DIV_MMC0 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    =
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-153  
    5.9.1.140 CLK_DIV_STAT_FSYS2 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0650, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:25] –=Reserved=0x0=
    DIV_MMC3_PRE=[24]=o=
    DIV_MMC3_PRE status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[23:17]=–=Reserved=0x0=
    DIV_MMC3=[16]=o=
    DIV_MMC3 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[15:9]=–=Reserved=0x0=
    DIV_MMC2_PRE=[8]=o=
    DIV_MMC2_PRE status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[7:1]=–=Reserved=0x0=
    DIV_MMC2=[0]=o=
    DIV_MMC2 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    =
    = 
    						
    							Samsung Confidential  
    Exynos 5250_UM 5 Clock Controller 
     5-154  
    5.9.1.141 CLK_DIV_STAT_PERIC0 
     Base Address: 0x1002_0000 
     Address = Base Address + 0x0658, Reset Value = 0x0000_0000 
    Name Bit Type Description Reset Value 
    RSVD [31:13] –=Reserved=0x0=
    DIV_UART3=[12]=o=
    DIV_UART3 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[11:9]=–=Reserved=0x0=
    DIV_UART2=[8]=o=
    DIV_UART2 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[7:5]=–=Reserved=0x0=
    DIV_UART1=[4]=o=
    DIV_UART1 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    RSVD=[3:1]=–=Reserved=0x0=
    DIV_UART0=[0]=o=
    DIV_UART0 status=
    0 = Stable=
    1 = Divider is changing=
    0x0=
    =
    = 
    						
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