Samsung Exynos 5 User Manual

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-167  
4.4.1.240 EXT_INT42CON 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0E08, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
EXT_INT42=
_CON[7]=[30:28]=RW=
Setting the signaling method=of EXT_INT42[7]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT42=
_CON[6]=[26:24]=RW=
Setting the signaling method=of EXT_INT42[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to=0x7 = Reserved=
0x0=
RSVD=[23]=–=Reserved=0x0=
EXT_INT42=
_CON[5]=[22:20]=RW=
Setting the signaling method=of EXT_INT42[5]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7== Reserved=
0x0=
RSVD=[19]=–=Reserved=0x0=
EXT_INT42=
_CON[4]=[18:16]=RW=
Setting the signaling method=of EXT_INT42[4]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 ==Reserved=
0x0=
RSVD=[15]=–=Reserved=0x0=
EXT_INT42=
_CON[3]=[14:12]=RW=
Setting the signaling method=of EXT_INT42[3]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[11]=–=Reserved=0x0=
EXT_INT42=[10:8]=RW=Setting the signaling method=of EXT_INT42[2]=0x0= 
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-168  
Name Bit Type Description Reset Value 
_CON[2] 0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
RSVD [7] – Reserved 0x0 
EXT_INT42 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT42[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT42 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT42[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-169  
4.4.1.241 EXT_INT43CON 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0E0C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
EXT_INT43=
_CON[7]=[30:28]=RW=
Setting the signaling method=of EXT_INT43[7]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT43=
_CON[6]=[26:24]=RW=
Setting the signaling method=of EXT_INT43[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[23]=–=Reserved=0x0=
EXT_INT43=
_CON[5]=[22:20]=RW=
Setting the signaling method=of EXT_INT43[5]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[19]=–=Reserved=0x0=
EXT_INT43=
_CON[4]=[18:16]=RW=
Setting the signaling method of EXT_INT43[4]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[15]=–=Reserved=0x0=
EXT_INT43=
_CON[3]=[14:12]=RW=
Setting the signaling method of EXT_INT43[3]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[11]=–=Reserved=0x0=
EXT_INT43=[10:8]=RW=Setting the signaling method=of EXT_INT43[2]=0x0= 
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-170  
Name Bit Type Description Reset Value 
_CON[2] 0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
RSVD [7] – Reserved 0x0 
EXT_INT43 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT43[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT43 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT43[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-171  
4.4.1.242 EXT_INT40_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0E80, Reset Value = 0x8080_8080 
Name Bit Type Description Reset Value 
FLTEN14[3] [31] RW 
Enables Filter for EXT_INT40[3] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL14[3] [30] RW 
Selects Filter for EXT_INT40[3] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH14[3] [29:24] RW Filtering width of EXT_INT40[3] 
This value is valid when FLTSEL14 (of EXT_INT40) is 0x1. 0x00 
FLTEN14[2] [23] RW 
Enables Filter for EXT_INT40[2] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL14[2] [22] RW 
Selects Filter for EXT_INT40[2] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH14[2] [21:16] RW Filtering width of EXT_INT40[2] 
This value is valid when FLTSEL14 (of EXT_INT40) is 0x1. 0x00 
FLTEN14[1] [15] RW 
Enables Filter for EXT_INT40[1] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL14[1] [14] RW 
Selects Filter for EXT_INT40[1] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH14[1] [13:8] RW Filtering width of EXT_INT40[1] 
This value is valid when FLTSEL14 (of EXT_INT40) is 0x1. 0x00 
FLTEN14[0] [7] RW 
Enables Filter for EXT_INT40[0] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL14[0] [6] RW 
Selects Filter for EXT_INT40[0] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH14[0] [5:0] RW Filtering width of EXT_INT40[0] 
This value is valid when FLTSEL14 (of EXT_INT40) is 0x1. 0x00 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-172  
4.4.1.243 EXT_INT40_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0E84, Reset Value = 0x8080_8080 
Name Bit Type Description Reset Value 
FLTEN14[7] [31] RW 
Enables Filter for EXT_INT40[7] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL14[7] [30] RW 
Selects Filter for EXT_INT40[7] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH14[7] [29:24] RW Filtering width of EXT_INT40[7] 
This value is valid when FLTSEL14 (of EXT_INT40) is 0x1. 0x00 
FLTEN14[6] [23] RW 
Enables Filter for EXT_INT40[6] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL14[6] [22] RW 
Selects Filter for EXT_INT40[6] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH14[6] [21:16] RW Filtering width of EXT_INT40[6] 
This value is valid when FLTSEL14 (of EXT_INT40) is 0x1. 0x00 
FLTEN14[5] [15] RW 
Enables Filter for EXT_INT40[5] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL14[5] [14] RW 
Selects Filter for EXT_INT40[5] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH14[5] [13:8] RW Filtering width of EXT_INT40[5] 
This value is valid when FLTSEL14 (of EXT_INT40) is 0x1. 0x00 
FLTEN14[4] [7] RW 
Enables Filter for EXT_INT40[4] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL14[4] [6] RW 
Selects Filter for EXT_INT40[4] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH14[4] [5:0] RW Filtering width of EXT_INT40[4] 
This value is valid when FLTSEL14 (of EXT_INT40) is 0x1. 0x00 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-173  
4.4.1.244 EXT_INT41_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0E88, Reset Value = 0x8080_8080 
Name Bit Type Description Reset Value 
FLTEN15[3] [31] RW 
Enables Filter for EXT_INT41[3] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL15[3] [30] RW 
Selects Filter for EXT_INT41[3] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH15[3] [29:24] RW Filtering width of EXT_INT41[3] 
This value is valid when FLTSEL15 (of EXT_INT41) is 0x1. 0x00 
FLTEN15[2] [23] RW 
Enables Filter for EXT_INT41[2] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL15[2] [22] RW 
Selects Filter for EXT_INT41[2] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH15[2] [21:16] RW Filtering width of EXT_INT41[2] 
This value is valid when FLTSEL15 (of EXT_INT41) is 0x1. 0x00 
FLTEN15[1] [15] RW 
Enables Filter for EXT_INT41[1] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL15[1] [14] RW 
Selects Filter for EXT_INT41[1] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH15[1] [13:8] RW Filtering width of EXT_INT41[1] 
This value is valid when FLTSEL15 (of EXT_INT41) is 0x1. 0x00 
FLTEN15[0] [7] RW 
Enables Filter for EXT_INT41[0] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL15[0] [6] RW 
Selects Filter for EXT_INT41[0] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH15[0] [5:0] RW Filtering width of EXT_INT41[0] 
This value is valid when FLTSEL15 (of EXT_INT41) is 0x1. 0x00 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-174  
4.4.1.245 EXT_INT41_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0E8C, Reset Value = 0x8080_8080 
Name Bit Type Description Reset Value 
FLTEN15[7] [31] RW 
Enables Filter for EXT_INT41[7] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL15[7] [30] RW 
Selects Filter for EXT_INT41[7] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH15[7] [29:24] RW Filtering width of EXT_INT41[7] 
This value is valid when FLTSEL15 (of EXT_INT41) is 0x1. 0x00 
FLTEN15[6] [23] RW 
Enables Filter for EXT_INT41[6] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL15[6] [22] RW 
Selects Filter for EXT_INT41[6] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH15[6] [21:16] RW Filtering width of EXT_INT41[6] 
This value is valid when FLTSEL15 (of EXT_INT41) is 0x1. 0x00 
FLTEN15[5] [15] RW 
Enables Filter for EXT_INT41[5] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL15[5] [14] RW 
Selects Filter for EXT_INT41[5] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH15[5] [13:8] RW Filtering width of EXT_INT41[5] 
This value is valid when FLTSEL15 (of EXT_INT41) is 0x1. 0x00 
FLTEN15[4] [7] RW 
Enables Filter for EXT_INT41[4] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL15[4] [6] RW 
Selects Filter for EXT_INT41[4] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH15[4] [5:0] RW Filtering width of EXT_INT41[4] 
This value is valid when FLTSEL15 (of EXT_INT41) is 0x1. 0x00 
  
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-175  
4.4.1.246 EXT_INT42_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0E90, Reset Value = 0x8080_8080 
Name Bit Type Description Reset Value 
FLTEN16[3] [31] RW 
Enables Filter for EXT_INT42[3] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL16[3] [30] RW 
Selects Filter for EXT_INT42[3] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH16[3] [29:24] RW Filtering width of EXT_INT42[3] 
This value is valid when FLTSEL16 (of EXT_INT42) is 0x1. 0x00 
FLTEN16[2] [23] RW 
Enables Filter for EXT_INT42[2] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL16[2] [22] RW 
Selects Filter for EXT_INT42[2] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH16[2] [21:16] RW Filtering width of EXT_INT42[2] 
This value is valid when FLTSEL16 (of EXT_INT42) is 0x1. 0x00 
FLTEN16[1] [15] RW 
Enables Filter for EXT_INT42[1] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL16[1] [14] RW 
Selects Filter for EXT_INT42[1] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH16[1] [13:8] RW Filtering width of EXT_INT42[1] 
This value is valid when FLTSEL16 (of EXT_INT42) is 0x1. 0x00 
FLTEN16[0] [7] RW 
Enables Filter for EXT_INT42[0] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL16[0] [6] RW 
Selects Filter for EXT_INT42[0] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH16[0] [5:0] RW Filtering width of EXT_INT42[0] 
This value is valid when FLTSEL16 (of EXT_INT42) is 0x1. 0x00 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-176  
4.4.1.247 EXT_INT42_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0E94, Reset Value = 0x8080_8080 
Name Bit Type Description Reset Value 
FLTEN16[7] [31] RW 
Enables Filter for EXT_INT42[7] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL16[7] [30] RW 
Selects Filter for EXT_INT42[7] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH16[7] [29:24] RW Filtering width of EXT_INT42[7] 
This value is valid when FLTSEL16 (of EXT_INT42) is 0x1. 0x00 
FLTEN16[6] [23] RW 
Enables Filter for EXT_INT42[6] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL16[6] [22] RW 
Selects Filter for EXT_INT42[6] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH16[6] [21:16] RW Filtering width of EXT_INT42[6] 
This value is valid when FLTSEL16 (of EXT_INT42) is 0x1. 0x00 
FLTEN16[5] [15] RW 
Enables Filter for EXT_INT42[5] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL16[5] [14] RW 
Selects Filter for EXT_INT42[5] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH16[5] [13:8] RW Filtering width of EXT_INT42[5] 
This value is valid when FLTSEL16 (of EXT_INT42) is 0x1. 0x00 
FLTEN16[4] [7] RW 
Enables Filter for EXT_INT42[4] 
0x0 = Disables 
0x1 = Enables 
0x1 
FLTSEL16[4] [6] RW 
Selects Filter for EXT_INT42[4] 
0x0 = Delays filter 
0x1 = Digital filter (clock count) 
0x0 
FLTWIDTH16[4] [5:0] RW Filtering width of EXT_INT42[4] 
This value is valid when FLTSEL16 (of EXT_INT42) is 0x1. 0x00