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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-175  
5.9.1.165 CLK_GATE_BLOCK 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0980, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0xFF_FFFF=
CLK_ACm=x7]=RW=
Gating all=Clocks for=ACP_BLK (ACPG2D)=
0 ==Masks=
1 = Passes=
0x1=
RSVD=x6]=–=Reserved=0x1=
CLK_DISP1=[5]=RW=
Gating all=Clocks for=DISP1_BLK (FIMD1, MIE1, 
DSIM1)=
0 = Masks=
1 = Passes=
0x1=
RSVD=x4]=–=Reserved=0x1=
CLK_GSCL=[3]=RW=
Gating all=Clocks for=GSCL_BLK (GSCL0, 1, 2, 3)=
0 = Masks=
1 = Passes=
0x1=
CLK_GEN=[2]=RW=
Gating all clocks for GEN_BLK (ROTATOR, JPEG=
and SYSTEM BUS through GEN BLK such as=
CMU, PMU SFR access)=
Should=not set this field as 0. This causes system 
hang up when F/W accesses CMU, PMU SFRs.=
0 = Masks=
1 = Passes=
0x1=
CLK_G3a=[1]=RW=
Gating all=Clocks for=G3a_BLK (G3a)=
0 = Masks=
1 = Passes=
0x1=
CLK_MFC=[0]=RW=
Gating all=Clocks for=MFC_BLK=MFC)=
0 = Masks=
1 = Passes=
0x1=
=
5.9.1.166 MCUIOP_PWR_CTRL 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x09A0, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
CSCLK_AUTO=
_ENB_IN_DEBUd=[0]=RW=
Force CoreSight Clocks to toggle when debugger is=
attached=
0 = Disables=
1 = Enables=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-176  
5.9.1.167 CLKOUT_CMU_TOP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = EPLL_FOUT=
00001 = VPLL_FOUT=
00010 = CPLL_FOUT=
00011 = SCLK_HDMI24M=
00100 = SCLK_DPTXPHY=
00101 = SCLK_UHOSTPHY=
00110 = SCLK_HDMIPHY=
00111 = AUDIOCDCLK0=
01000 = AUDIOCDCLK1=
01001 = AUDIOCDCLK2=
01010 = SPDIF_EXTCLK=
01011 = ACLK_400_G3a=
01100 = ACLK_333=
01101 = ACLK_266=
01110 = GPLL_FOUT=
01111 = ACLK_400_ISP=
10000 = ACLK_400_IOP=
10001 = SCLK_JPEd=
10010 = RX_HALF_BYTE_CLK_A=
10011 = RX_HALF_BYTE_CLK_B=
10100 = CAM_A_PCLK=
10101 = CAM_B_PCLK=
10110 = S_RXBYTECLKHS0_2i=
10111 = S_RXBYTECLKHS0_4i=
11000 = ACLK_300_DISP1=
11001 = ACLK_300_GSCi=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-177  
5.9.1.168 CLKOUT_CMU_TOP_DIV_STAT 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.169 CLK_SRC_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4200, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
MUX_ATCLK_LEu=[0]=RW=
Control MUu_ATCLK_LEX, which is the source 
clock of MOUT_ATCLK_LEu=
0== ACLK_200=
1 = ACLK_266=
0x0=
=
5.9.1.170 CLK_MUX_STAT_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4400, Reset Value = 0x0000_0001 
Name Bit Type Description Reset Value 
RSVD [31:3] –=Reserved=0x0=
ATCLK_LEX_SEi=[2:0]=o=
Selection signal status of MUX_ATCLK_LEX=
001== ACLK_200=
010 = ACLK_266=
1xx = On changing=
0x1=
=
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Exynos 5250_UM 5 Clock Controller 
 5-178  
5.9.1.171 CLK_DIV_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:11] –=Reserved=0x0=
ATCLK_LEu=
_RATIO=[10:8]=RW=
ATCLK_LEX clock divider oatio=
ATCLK_LEu=
= MOUT_ATCLK_LEX/(ATCLK_LEX_RATIO + 1)=
0x0=
RSVD=[7]=–=Reserved=0x0=
PCLK_LEX=
_RATIO=[6:4]=RW=
PCLK_LEX clock divider=oatio=
PCLK_LEX=
= ACLK_266 /(PCLK_LEX_RATIO + 1)=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.172 CLK_DIV_STAT_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
DIV_ATCLK_LEu=[8]=o=
DIV_ATCLK_LEX status=
0== Stable=
1 = Divider is changing=
0x0=
RSVD=[7:5]=–=Reserved=0x0=
DIV_PCLK_LEX=[4]=o=
DIV_PCLK_LEX status=
0== Stable=
1 = Divider is changing=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-179  
5.9.1.173 CLK_GATE_IP_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4800, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
5.9.1.174 CLKOUT_CMU_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = ACLK_266=
00001 = APLL_DLEX=
00010 = ACLK_PLEX=
0x0=
=
5.9.1.175 CLKOUT_CMU_LEX_DIV_STAT 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-180  
5.9.1.176 CLK_DIV_R0X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x8500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0x0=
PCLK_R0X_RATIO=[6:4]=RW=
DIs_PR0u=Clock divider Ratio=
PCLK_R0u=
= ACLK_26S/(PCLK_R0X_RATIO + 1)=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.177 CLK_DIV_STAT_R0X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x8600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
DIV_PCLK_R0X=[4]=o=
DIs_PR0u=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.178 CLK_GATE_IP_R0X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x8800, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-181  
5.9.1.179 CLKOUT_CMU_R0X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x8A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = ACLK_266=
00001 = APLL_DR0X=
00010 = ACLK_PR0X=
0x0=
=
5.9.1.180 CLKOUT_CMU_R0X_DIV_STAT 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x8A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT=Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-182  
5.9.1.181 CLK_DIV_R1X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0xC500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0x0=
PCLK_R1X_RATIO=[6:4]=RW=
DIs_PR1u=clock divider Ratio=
PCLK_R1u=
= ACLK_26S/(PCLK_R1X_RATIO + 1)=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.182 CLK_DIV_STAT_R1X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0xC600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
DIV_PCLK_R1X=[4]=o=
DIs_PR1u=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.183 CLK_GATE_IP_R1X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0xC800, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-183  
5.9.1.184 CLKOUT_CMU_R1X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0xCA00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = ACLK_266=
00001 = APLL_DR1X=
00010 = ACLK_PR1X=
0x0=
=
5.9.1.185 CLKOUT_CMU_R1X_DIV_STAT 
 Base Address: 0x1002_0000 
 Address = Base Address + 0xCA04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.186 BPLL_LOCK 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0010, Reset Value = 0x0000_0FFF 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required period=(in cycles) to generate a stable=
clock output.=
The maximum lock time can be up to 250= PDIV 
cycles of PLLs FIN (XXTI). 
0xF_FFFF
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Exynos 5250_UM 5 Clock Controller 
 5-184  
5.9.1.187 BPLL_CON0 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0110, Reset Value = 0x00C8_0601 
Name Bit Type Description Reset Value 
ENABLE [31] RW 
PLL Enable control 
0 = Disables 
1 = Enables 
0x0 
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL Locking indication=
0 = Unlocks=
1 = Locks=
0x0=
RSVD=[28:26]=–=Reserved=0x0=
MDIV=[25:16]=RW=PLL M Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=PLL P Divide Value=0xS=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=PLL S Divide Value=0x1=
=
The reset value of=BPLL_CON0=generates 400=MHz output clock=for the input clock frequency of=24=MHz.=
Equation to calculate the=output frequency=is:=
 FOUT = MDIV  FIN/(PDIV  2SDIV) 
 MDIV, PDIV, SDIV for BPLL should conform to these conditions: 
 PDIV: 1  PDIV  63 
 MDIV: 64  MDIV  1023 
 SDIV: 0  SDIV  5 
 Fref (= FIN/PDIV): 1 MHz  Fref  12 MHz 
 FVCO (= MDIV  FIN/PDIV): 700 MHz  FVCO  1600 MHz 
 FOUT: 21.9 MHz  FOUT  1600 MHz 
Do not set the value of PDIV [5:0] or MDIV [9:0] to all zeros 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on 
recommended PMS values. 
SDIV[2:0] controls division ratio of Scaler as described in Table 5-15.
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