Samsung Exynos 5 User Manual

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Exynos 5250_UM 6 Interrupt Controller 
 6-11  
SPI Port No Id Int_e_combiner Interrupt Source Source Block 
IntG2_1 SYSMMU_GSCL0[1] – 
IntG2_0 SYSMMU_GSCL0[0] – 
1 33 
IntG1_7 CPU_nCNTVIRQ[0] – 
IntG1_6 CPU_nCNTPSIRQ[0] – 
IntG1_5 CPU_nCNTPSNIRQ[0] – 
IntG1_4 CPU_nCNTHPIRQ[0] – 
IntG1_3 CPU_nCTIIRQ[0] – 
IntG1_2 CPU_nPMUIRQ[0] – 
IntG1_1 CPU_PARITYFAILSCU[0] – 
IntG1_0 CPU_PARITYFAIL0 – 
0 32 
IntG0_7 TZASC_XR1BXW – 
IntG0_6 TZASC_XR1BXR – 
IntG0_5 TZASC_XLBXW – 
IntG0_4 TZASC_XLBXR – 
IntG0_3 TZASC_DRBXW – 
IntG0_2 TZASC_DRBXR – 
IntG0_1 TZASC_CBXW – 
IntG0_0 TZASC_CBXR – 
  
						

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Exynos 5250_UM 6 Interrupt Controller 
 6-12  
Table 6-4   External GIC Interrupt Table (PPI[15:0]) 
PPI Port No ID Interrupt Source Source Block 
15 31 – – 
14 30 nCNTPNSIRQ CPU 
13 29 nCNTPSIRQ CPU 
12 28 – – 
11 27 nCNTVIRQ CPU 
10 26 nCNTHPIRQ CPU 
9 25 Virtual maintenance interrupt GIC 
8 24 – – 
7 23 – – 
6 22 – – 
5 21 – – 
4 20 – – 
3 19 – – 
2 18 – – 
1 17 – – 
0 16 – – 
 
  
						

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Exynos 5250_UM 6 Interrupt Controller 
 6-13  
6.3 Register Description 
6.3.1 Register Map Summary 
 Base_Address_D = 0x1048_1000 
Register Offset Description Reset Value 
Distributor Register Map 
GICD_CTLR 0x0000 Distributor control register 0x0000_0000 
GICD_TYPER 0x0004 Interrupt controller type register 0x0000_FC24 
GICD_IIDR 0x0008 Distributor implementer identification register 0x0200_043B 
GICD_IGROUPR0 0x0080 Interrupt security registers (SGI, PPI) 0x0000_0000 
GICD_IGROUPR1 0x0084 Interrupt security registers (SPI[31:0]) 0x0000_0000 
GICD_IGROUPR2 0x0088 Interrupt security registers (SPI[63:32]) 0x0000_0000 
GICD_IGROUPR3 0x008C Interrupt security registers (SPI[95:64]) 0x0000_0000 
GICD_IGROUPR4 0x0090 Interrupt security registers (SPI[127:96]) 0x0000_0000 
GICD_ISENABLER0 0x0100 Interrupt set-enable register (SGI, PPI) 0x0000_FFFF 
GICD_ISENABLER1 0x0104 Interrupt set-enable register (SPI[31:0]) 0x0000_0000 
GICD_ISENABLER2 0x0108 Interrupt set-enable register (SPI[63:32]) 0x0000_0000 
GICD_ISENABLER3 0x010C Interrupt set-enable register (SPI[95:64]) 0x0000_0000 
GICD_ISENABLER4 0x0110 Interrupt set-enable register (SPI[127:96]) 0x0000_0000 
GICD_ICENABLER0 0x0180 Interrupt clear-enable register (SGI, PPI) 0x0000_FFFF 
GICD_ICENABLER1 0x0184 Interrupt clear-enable register (SPI[31:0]) 0x0000_0000 
GICD_ICENABLER2 0x0188 Interrupt clear-enable register (SPI[63:32]) 0x0000_0000 
GICD_ICENABLER3 0x018C Interrupt clear-enable register (SPI[95:64]) 0x0000_0000 
GICD_ICENABLER4 0x0190 Interrupt clear-enable register (SPI[127:96]) 0x0000_0000 
GICD_ISPENDR0 0x0200 Interrupt pending-set register (SGI, PPI) 0x0000_0000 
GICD_ISPENDR1 0x0204 Interrupt pending-set register (SPI[31:0]) 0x0000_0000 
GICD_ISPENDR2 0x0208 Interrupt pending-set register (SPI[63:32]) 0x0000_0000 
GICD_ISPENDR3 0x020C Interrupt pending-set register (SPI[95:64]) 0x0000_0000 
GICD_ISPENDR4 0x0210 Interrupt pending-set register (SPI[127:96]) 0x0000_0000 
GICD_ICPENDR0 0x0280 Interrupt pending-clear register (SGI, PPI) 0x0000_0000 
GICD_ICPENDR1 0x0284 Interrupt pending-clear register (SPI[31:0]) 0x0000_0000 
GICD_ICPENDR2 0x0288 Interrupt pending-clear register (SPI[63:32]) 0x0000_0000 
GICD_ICPENDR3 0x028C Interrupt pending-clear register (SPI[95:64]) 0x0000_0000 
GICD_ICPENDR4 0x0290 Interrupt pending-clear register (SPI[127:96]) 0x0000_0000 
GICD_ISACTIVER0 0x0300 Interrupt set-active registers (SGI, PPI) 0x0000_0000 
GICD_ISACTIVER1 0x0304 Interrupt set-active registers (SPI[31:0]) 0x0000_0000 
GICD_ISACTIVER2 0x0308 Interrupt set-active registers (SPI[63:32]) 0x0000_0000 
GICD_ISACTIVER3 0x030C Interrupt set-active registers (SPI[95:64]) 0x0000_0000  
						

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Exynos 5250_UM 6 Interrupt Controller 
 6-14  
Register Offset Description Reset Value 
GICD_ISACTIVER4 0x0310 Interrupt set-active registers (SPI[127:96]) 0x0000_0000 
GICD_ICACTIVER0 0x0380 Interrupt clear-active registers (SGI, PPI) 0x0000_0000 
GICD_ICACTIVER1 0x0384 Interrupt clear-active registers (SPI[31:0]) 0x0000_0000 
GICD_ICACTIVER2 0x0388 Interrupt clear-active registers (SPI[63:32]) 0x0000_0000 
GICD_ICACTIVER3 0x038C Interrupt clear-active registers (SPI[95:64]) 0x0000_0000 
GICD_ICACTIVER4 0x0390 Interrupt clear-active registers (SPI[127:96]) 0x0000_0000 
GICD_IPRIORITYR0 0x0400 Priority level register (SGI[3:0]) 0x0000_0000 
GICD_IPRIORITYR1 0x0404 Priority level register (SGI[7:4]) 0x0000_0000 
GICD_IPRIORITYR2 0x0408 Priority level register (SGI[11:8]) 0x0000_0000 
GICD_IPRIORITYR3 0x040C Priority level register (SGI[15:12]) 0x0000_0000 
GICD_IPRIORITYR4 0x0410 Priority level register (PPI[3:0]) 0x0000_0000 
GICD_IPRIORITYR5 0x0414 Priority level register (PPI[7:4]) 0x0000_0000 
GICD_IPRIORITYR6 0x0418 Priority level register (PPI[11:8]) 0x0000_0000 
GICD_IPRIORITYR7 0x041C Priority level register (PPI[15:12]) 0x0000_0000 
GICD_IPRIORITYR8 0x0420 Priority level register (SPI[3:0]) 0x0000_0000 
GICD_IPRIORITYR9 0x0424 Priority level register (SPI[7:4]) 0x0000_0000 
GICD_IPRIORITYR10 0x0428 Priority level register (SPI[11:8]) 0x0000_0000 
GICD_IPRIORITYR11 0x042C Priority level register (SPI[15:12]) 0x0000_0000 
GICD_IPRIORITYR12 0x0430 Priority level register (SPI[19:16]) 0x0000_0000 
GICD_IPRIORITYR13 0x0434 Priority level register (SPI[23:20]) 0x0000_0000 
GICD_IPRIORITYR14 0x0438 Priority level register (SPI[27:24]) 0x0000_0000 
GICD_IPRIORITYR15 0x043C Priority level register (SPI[31:28]) 0x0000_0000 
GICD_IPRIORITYR16 0x0440 Priority level register (SPI[35:32]) 0x0000_0000 
GICD_IPRIORITYR17 0x0444 Priority level register (SPI[39:36]) 0x0000_0000 
GICD_IPRIORITYR18 0x0448 Priority level register (SPI[43:40]) 0x0000_0000 
GICD_IPRIORITYR19 0x044C Priority level register (SPI[47:44]) 0x0000_0000 
GICD_IPRIORITYR20 0x0450 Priority level register (SPI[51:48]) 0x0000_0000 
GICD_IPRIORITYR21 0x0454 Priority level register (SPI[55:52]) 0x0000_0000 
GICD_IPRIORITYR22 0x0458 Priority level register (SPI[59:56]) 0x0000_0000 
GICD_IPRIORITYR23 0x045C Priority level register (SPI[63:60]) 0x0000_0000 
GICD_IPRIORITYR24 0x0460 Priority level register (SPI[67:64]) 0x0000_0000 
GICD_IPRIORITYR25 0x0464 Priority level register (SPI[71:68]) 0x0000_0000 
GICD_IPRIORITYR26 0x0468 Priority level register (SPI[75:72]) 0x0000_0000 
GICD_IPRIORITYR27 0x046C Priority level register (SPI[79:76]) 0x0000_0000 
GICD_IPRIORITYR28 0x0470 Priority level register (SPI[83:80]) 0x0000_0000 
GICD_IPRIORITYR29 0x0474 Priority level register (SPI[87:84]) 0x0000_0000 
GICD_IPRIORITYR30 0x0478 Priority level register (SPI[91:98]) 0x0000_0000  
						

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Exynos 5250_UM 6 Interrupt Controller 
 6-15  
Register Offset Description Reset Value 
GICD_IPRIORITYR31 0x047C Priority level register (SPI[95:92]) 0x0000_0000 
GICD_IPRIORITYR32 0x0480 Priority level register (SPI[99:96]) 0x0000_0000 
GICD_IPRIORITYR33 0x0484 Priority level register (SPI[103:100]) 0x0000_0000 
GICD_IPRIORITYR34 0x0488 Priority level register (SPI[107:104]) 0x0000_0000 
GICD_IPRIORITYR35 0x048C Priority level register (SPI[111:108]) 0x0000_0000 
GICD_IPRIORITYR36 0x0490 Priority level register (SPI[115:112]) 0x0000_0000 
GICD_IPRIORITYR37 0x0494 Priority level register (SPI[119:116]) 0x0000_0000 
GICD_IPRIORITYR38 0x0498 Priority level register (SPI[123:120]) 0x0000_0000 
GICD_IPRIORITYR39 0x049C Priority level register (SPI[127:124]) 0x0000_0000 
GICD_ITARGETSR0 0x0800 Processor targets register (SGI[3:0]) 0x0101_0101 
GICD_ITARGETSR1 0x0804 Processor targets register (SGI[7:4]) 0x0101_0101 
GICD_ITARGETSR2 0x0808 Processor targets register (SGI[11:8]) 0x0101_0101 
GICD_ITARGETSR3 0x080C Processor targets register (SGI[15:12]) 0x0101_0101 
GICD_ITARGETSR4 0x0810 Processor targets register (PPI[3:0]) 0x0000_0000 
GICD_ITARGETSR5 0x0814 Processor targets register (PPI[7:4]) 0x0000_0000 
GICD_ITARGETSR6 0x0818 Processor targets register (PPI[11:8]) 0x0101_0100 
GICD_ITARGETSR7 0x081C Processor targets register (PPI[15:12]) 0x0101_0101 
GICD_ITARGETSR8 0x0820 Processor targets register (SPI[3:0]) 0x0000_0000 
GICD_ITARGETSR9 0x0824 Processor targets register (SPI[7:4]) 0x0000_0000 
GICD_ITARGETSR10 0x0828 Processor targets register (SPI[11:8]) 0x0000_0000 
GICD_ITARGETSR11 0x082C Processor targets register (SPI[15:12]) 0x0000_0000 
GICD_ITARGETSR12 0x0830 Processor targets register (SPI[19:16]) 0x0000_0000 
GICD_ITARGETSR13 0x0834 Processor targets register (SPI[23:20]) 0x0000_0000 
GICD_ITARGETSR14 0x0838 Processor targets register (SPI[27:24]) 0x0000_0000 
GICD_ITARGETSR15 0x083C Processor targets register (SPI[31:28]) 0x0000_0000 
GICD_ITARGETSR16 0x0840 Processor targets register (SPI[35:32]) 0x0000_0000 
GICD_ITARGETSR17 0x0844 Processor targets register (SPI[39:36]) 0x0000_0000 
GICD_ITARGETSR18 0x0848 Processor targets register (SPI[43:40]) 0x0000_0000 
GICD_ITARGETSR19 0x084C Processor targets register (SPI[47:44]) 0x0000_0000 
GICD_ITARGETSR20 0x0850 Processor targets register (SPI[51:48]) 0x0000_0000 
GICD_ITARGETSR21 0x0854 Processor targets register (SPI[55:52]) 0x0000_0000 
GICD_ITARGETSR22 0x0858 Processor targets register (SPI[59:56]) 0x0000_0000 
GICD_ITARGETSR23 0x085C Processor targets register (SPI[63:60]) 0x0000_0000 
GICD_ITARGETSR24 0x0860 Processor targets register (SPI[67:64]) 0x0000_0000 
GICD_ITARGETSR25 0x0864 Processor targets register (SPI[71:68]) 0x0000_0000 
GICD_ITARGETSR26 0x0868 Processor targets register (SPI[75:72]) 0x0000_0000 
GICD_ITARGETSR27 0x086C Processor targets register (SPI[79:76]) 0x0000_0000  
						

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Exynos 5250_UM 6 Interrupt Controller 
 6-16  
Register Offset Description Reset Value 
GICD_ITARGETSR28 0x0870 Processor targets register (SPI[83:80]) 0x0000_0000 
GICD_ITARGETSR29 0x0874 Processor targets register (SPI[87:84]) 0x0000_0000 
GICD_ITARGETSR30 0x0878 Processor targets register (SPI[91:98]) 0x0000_0000 
GICD_ITARGETSR31 0x087C Processor targets register (SPI[95:92]) 0x0000_0000 
GICD_ITARGETSR32 0x0880 Processor targets register (SPI[99:96]) 0x0000_0000 
GICD_ITARGETSR33 0x0884 Processor targets register (SPI[103:100]) 0x0000_0000 
GICD_ITARGETSR34 0x0888 Processor targets register (SPI[107:104]) 0x0000_0000 
GICD_ITARGETSR35 0x088C Processor targets register (SPI[111:108]) 0x0000_0000 
GICD_ITARGETSR36 0x0890 Processor targets register (SPI[115:112]) 0x0000_0000 
GICD_ITARGETSR37 0x0894 Processor targets register (SPI[119:116]) 0x0000_0000 
GICD_ITARGETSR38 0x0898 Processor targets register (SPI[123:120]) 0x0000_0000 
GICD_ITARGETSR39 0x089C Processor targets register (SPI[127:124]) 0x0000_0000 
GICD_ICFGR0 0x0C00 Interrupt configuration register (SGI[15:0]) 0xAAAA_AAAA 
GICD_ICFGR1 0x0C04 Interrupt configuration register (PPI[15:0]) 0x5554_0000 
GICD_ICFGR2 0x0C08 Interrupt configuration register (SPI[15:0]) 0x5555_5555 
GICD_ICFGR3 0x0C0C Interrupt configuration register (SPI[31:16]) 0x5555_5555 
GICD_ICFGR4 0x0C10 Interrupt configuration register (SPI[47:32]) 0x5555_5555 
GICD_ICFGR5 0x0C14 Interrupt configuration register (SPI[63:48]) 0x5555_5555 
GICD_ICFGR6 0x0C18 Interrupt configuration register (SPI[79:64]) 0x5555_5555 
GICD_ICFGR7 0x0C1C Interrupt configuration register (SPI[95:80]) 0x5555_5555 
GICD_ICFGR8 0x0C20 Interrupt configuration register (SPI[111:95]) 0x5555_5555 
GICD_ICFGR9 0x0C24 Interrupt configuration register (SPI[127:112]) 0x5555_5555 
GICD_PPISR 0x0D00 PPI status register 0x0000_0000 
GICD_SPISR0 0x0D04 SPI[31:0] status register 0x0000_0000 
GICD_SPISR1 0x0D08 SPI[63:32] status register 0x0000_0000 
GICD_SPISR2 0x0D0C SPI[95:64] status register 0x0000_0000 
GICD_SPISR3 0x0D10 SPI[127:96] status register 0x0000_0000 
GICD_SGIR 0x0F00 Software generated interrupt register Undefined 
GICD_CPENDSGIR0 0x0F10 SGI[3:0] clear-pending registers 0x0000_0000 
GICD_CPENDSGIR1 0x0F14 SGI[7:4] clear-pending registers 0x0000_0000 
GICD_CPENDSGIR2 0x0F18 SGI[11:8] clear-pending registers 0x0000_0000 
GICD_CPENDSGIR3 0x0F1C SGI[15:12] clear-pending registers 0x0000_0000 
GICD_SPENDSGIR0 0x0F20 SGI[3:0] set-pending registers 0x0000_0000 
GICD_SPENDSGIR1 0x0F24 SGI[7:4] set-pending registers 0x0000_0000 
GICD_SPENDSGIR2 0x0F28 SGI[11:8] set-pending registers 0x0000_0000 
GICD_SPENDSGIR3 0x0F2C SGI[15:12] set-pending registers 0x0000_0000 
GICD_PIDR4 0x0FD0 Peripheral ID 4 register 0x0000_0004  
						

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Exynos 5250_UM 6 Interrupt Controller 
 6-17  
Register Offset Description Reset Value 
GICD_PIDR5 0x0FD4 Peripheral ID 5 register 0x0000_0000 
GICD_PIDR6 0x0FD8 Peripheral ID 6 register 0x0000_0000 
GICD_PIDR7 0x0FDC Peripheral ID 7 register 0x0000_0000 
GICD_PIDR0 0x0FE0 Peripheral ID 0 register 0x0000_0090 
GICD_PIDR1 0x0FE4 Peripheral ID 1 register 0x0000_00B4 
GICD_PIDR2 0x0FE8 Peripheral ID 2 register 0x0000_002B 
GICD_PIDR3 0x0FEC Peripheral ID 3 register 0x0000_0000 
GICD_CIDR0 0x0FF0 Component ID 0 register 0x0000_000D 
GICD_CIDR1 0x0FF4 Component ID 1 register 0x0000_00F0 
GICD_CIDR2 0x0FF8 Component ID 2 register 0x0000_0005 
GICD_CIDR3 0x0FFC Component ID 3 register 0x0000_00B1 
 
 Base_Address_C = 0x1048_2000 
Register Offset Description Reset Value 
CPU Interface Register Map 
GICC_CTLR 0x0000 CPU interface control register 0x0000_0000 
GICC_PMR 0x0004 Interrupt priority mask register 0x0000_0000 
GICC_BPR 0x0008 Binary point register 0x0000_0002 
GICC_IAR 0x000C Interrupt acknowledge register 0x0000_03FF 
GICC_EOIR 0x0010 End of interrupt register Undefined 
GICC_RPR 0x0014 Running priority register 0x0000_00FF 
GICC_HPPIR 0x0018 Highest pending interrupt register 0x0000_03FF 
GICC_ABPR 0x001C Aliased binary point register 0x0000_0003 
GICC_AIAR 0x0020 Aliased interrupt acknowledge register 0x0000_03FF 
GICC_AEOIR 0x0024 Aliased end of interrupt register Undefined 
GICC_AHPPIR 0x0028 Aliased highest priority pending interrupt register 0x0000_03FF 
GICC_APR0 0x00D0 Active priority register 0x0000_0000 
GICC_NSAPR0 0x00E0 Non-secure active priority register 0x0000_0000 
GICC_IIDR 0x00FC CPU interface identification register 0x0202_043B 
GICC_DIR 0x1000 Deactivate interrupt register Undefined 
 
  
						

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Exynos 5250_UM 6 Interrupt Controller 
 6-18  
 Base_Address_V = 0x1048_4000 
Register Offset Description Reset Value 
Virtual Interface Control Register Map 
GICH_HCR 0x0000 Hypervisor control register 0x0000_0000 
GICH_VTR 0x0004 VGIC type register 0x9000_0003 
GICH_VMCR 0x0008 Virtual machine control register 0x004C_0000 
GICH_MISR 0x0010 Maintenance interrupt status register 0x0000_0000 
GICH_EISR0 0x0020 End of interrupt status register 0x0000_0000 
GICH_ELSR0 0x0030 Empty list register status register 0x0000_000F 
GICH_APR0 0x00F0 Active priority register 0x0000_0000 
GICH_LR0 0x0100 List register 0 0x0000_0000 
GICH_LR1 0x0104 List register 1 0x0000_0000 
GICH_LR2 0x0108 List register 2 0x0000_0000 
GICH_LR3 0x010C List register 3 0x0000_0000 
 
 Base_Address_VC = 0x1048_6000 
Register Offset Description Reset Value 
Virtual CPU Interface Register Map 
GICV_CTLR 0x0000 Virtual machine control register 0x0000_0000 
GICV_PMR 0x0004 VM priority mask register 0x0000_0000 
GICV_BPR 0x0008 VM binary point register 0x0000_0002 
GICV_IAR 0x000C VM interrupt acknowledge register 0x0000_03FF 
GICV_EOIR 0x0010 VM end of interrupt register Undefined 
GICV_RPR 0x0014 VM running priority register 0x0000_00FF 
GICV_HPPIR 0x0018 VM highest priority pending interrupt register 0x0000_03FF 
GICV_ABPR 0x001C VM aliased binary point register 0x0000_0003 
GICV_AIAR 0x0020 VM aliased interrupt acknowledge register 0x0000_03FF 
GICV_AEOIR 0x0024 VM aliased end of interrupt register Undefined 
GICV_AHPPIR 0x0028 VM aliased highest priority pending interrupt 
register 0x0000_03FF 
GICV_APR0 0x00D0 VM active priority register 0x0000_0000 
GICV_IIDR 0x00FC VM CPU interface identification register 0x0202043B 
GICV_DIR 0x1000 VM deactivate interrupt register Undefined 
NOTE: Please refer to the GIC Architecture Specification document for detailed register descriptions. 
  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-1  
7 Interrupt Combiner 
7.1 Overview 
The interrupt controller subsystem in Exynos 5250 consists of generic interrupt controllers and interrupt 
combiners. Some interrupt sources are grouped in Exynos 5250. The interrupt combiner combines several 
interrupt sources as a group. Several interrupt requests in a group, create a group interrupt request, which 
produces a single request signal. Therefore, the interrupt input sources of the generic interrupt controller consists 
of the group interrupt requests from the interrupt combiner and uncombined interrupt sources. 
 
7.2 Features 
The features for interrupt combiner are: 
 Supports 32 group interrupt outputs for the interrupt combiner 
 Provides Enable/Mask of each interrupt source in a group 
 Provides Status of each interrupt source in a group before interrupt masking 
 Provides Status of each interrupt source in a group after interrupt masking 
 Provides Status of each group interrupt output after interrupt masking and combining 
  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-2  
7.3 Interrupt Sources 
Table 7-1 lists the interrupt groups of interrupt combiner. 
Table 7-1   Interrupt Groups of Interrupt Combiner 
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
INTG0 TZASC 
[7] TZASC_XR1BXW 
SYSMEM 
[6] TZASC_XR1BXR 
[5] TZASC_XLBXW 
[4] TZASC_XLBXR 
[3] TZASC_DRBXW 
[2] TZASC_DRBXR 
[1] TZASC_CBXW 
[0] TZASC_CBXR 
INTG1 PARITYFAIL0/CPUCTI0/PMU0 
[7] CPU_nCNTVIRQ[0] 
CPU0 
[6] CPU_nCNTPSIRQ[0] 
[5] CPU_nCNTPSNIRQ[0] 
[4] CPU_nCNTHPIRQ[0] 
[3] CPU_nCTIIRQ[0] 
[2] CPU_nPMUIRQ[0] 
[1] CPU_PARITYFAILSCU[0] 
[0] CPU_PARITYFAIL0 
INTG2 SYSMMU[7:0] 
[7] SYSMMU_GSCL3[1] 
System MMU 
[6] SYSMMU_GSCL3[0] 
[5] SYSMMU_GSCL2[1] 
[4] SYSMMU_GSCL2[0] 
[3] SYSMMU_GSCL1[1] 
[2] SYSMMU_GSCL1[0] 
[1] SYSMMU_GSCL0[1] 
[0] SYSMMU_GSCL0[0] 
INTG3 SYSMMU[15:8] 
[7] SYSMMU_SCALERPISP[1] 
System MMU 
[6] SYSMMU_SCALERPISP[0] 
[5] SYSMMU_FIMC_LITE0[1] 
[4] SYSMMU_FIMC_LITE0[0] 
[3] SYSMMU_DISP1_M0[1] 
[2] SYSMMU_DISP1_M0[0] 
[1] SYSMMU_FIMC_LITE2[1] 
[0] SYSMMU_FIMC_LITE2[0]