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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-95  
5.9.1.75 CPLL_LOCK 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0020, Reset Value = 0x0000_0FFF 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required period=(in cycles)=to generate a stable=
clock output.=
The maximum lock time can be up to 250= PDIV 
cycles of PLLs FIN (XXTI). 
0xF_FFFF 
 
5.9.1.76 EPLL_LOCK 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0030, Reset Value = 0x0000_0FFF 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required period=(in cycles)=to generate a stable=
clock output.=
The maximum lock time can be up to 3000  PDIV 
cycles of PLLs FIN (XXTI). 
0xF_FFFF 
 
5.9.1.77 VPLL_LOCK 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0040, Reset Value = 0x0000_0FFF 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required period=(in cycles)=to generate a stable=
clock output.=
The maximum lock time can be up to 3000  PDIV 
cycles of PLLs FIN (XXTI). 
0xF_FFF
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Exynos 5250_UM 5 Clock Controller 
 5-96  
5.9.1.78 GPLL_LOCK 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0050, Reset Value = 0x0000_0FFF 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required period=(in cycles)=to generate a stable=
clock output.=
The maximum lock time can be up to 3000  PDIV 
cycles of PLLs FIN (XXTI). 
0xF_FFF
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Exynos 5250_UM 5 Clock Controller 
 5-97  
5.9.1.79 CPLL_CON0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0120, Reset Value = 0x00C8_0601 
Name Bit Type Description Reset Value 
ENABLE [31] RW 
PLL Enable control 
0 = Disables 
1 = Enables 
0x0 
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL Locking indication=
0 = Unlocks=
1 = Locks=
0x0=
RSVD=x28]=–=Reserved=0x0=
FSEL=[27]=RW=
Monitoring=Frequency Select pin=
0 = FVCO_OUT = FREc=
1 = FVCO_OUT = FVCl=
0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=PLL M Divide value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=PLL P Divide value=0xS=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=PLL S Divide Value=0x1=
=
The reset value of=CPLL_CON0=generates 400=MHz output clock=for the input clock frequency of=24=MHz.=
Equation to calculate the=output frequency=is:=
 FOUT = MDIV  FIN/(PDIV  2SDIV) 
MDIV, PDIV, SDIV for CPLL should conform to these conditions: 
 PDIV: 1  PDIV  63 
 MDIV: 64  MDIV  1023 
 SDIV: 0  SDIV  5 
 Fref (= FIN/PDIV): 2 MHz  Fref  12 MHz 
 FVCO (= MDIV  FIN/PDIV): 700 MHz  FVCO  1400 MHz 
 FOUT: 21.9 MHz  FOUT  1400 MHz 
Do not set the value of PDIV [5:0] or MDIV [9:0] to all zeros. 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on 
recommended PMS values. 
SDIV[2:0] controls division ratio of Scaler as described in Table 5-15.
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Exynos 5250_UM 5 Clock Controller 
 5-98  
5.9.1.80 CPLL_CON1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0124, Reset Value = 0x0020_3800 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x0=
DCC_ENB=[21]=RW=
Enables Duty Cycle Corrector=
(only for monitoring)=
0 ==Enables DCC=
1 = Disables DCC=
0x1=
AFC_ENB=x20]=RW=
Decides=whether AFC is enabled or not (Active-
low)=
0 ==Enables AFC=
1 = Disables AFC=
0x0=
RSVD=x19:17]=–=Reserved=0x0=
FEED_EN=[16]=RW=Enable pin for FEED_OUT (Active-high)=0x0=
LOCK_CON_OUT=[15:14]=RW=Lock detector setting of the output margin=0x0=
LOCK_CON_IN=[13:12]=RW=Lock detector setting of the input margin=0x3=
LOCK_CON_DLY=[11:8]=RW=Lock detector setting of the detection resolution=0x8=
RSVD=[7:5]=–=Reserved=0x0=
EXTAFC=[4:0]=RW=Enable pin for FVCO_OUT (Active-high)=0x0=
=
AFC automatically selects adaptive frequency curve of VCO using switched=current bank for:=
 Wide range  
 High phase noise (or Jitter) 
 Fast lock time 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on 
recommended AFC_ENB and EXTAFC values.
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Exynos 5250_UM 5 Clock Controller 
 5-99  
5.9.1.81 EPLL_CON0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0130, Reset Value = 0x0030_0301 
Name Bit Type Description Reset Value 
ENABLE [31] RW 
PLL Enable control 
0 = Disables 
1 = Enables 
0x0 
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL locking indication=
0 = Unlocks=
1 = Locks=
0x0=
RSVD=[28:25]=–=Reserved=0x0=
MDIV=[24:16]=RW=PLL M Divide Value=0x30=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=PLL P Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=PLL S Divide Value=0x1=
=
The reset value of EPLL_CON0 generates 192 MHz output clock=for=the input clock frequency of=24=MHz.=
Equation to calculate the=output frequency=is:=
 FOUT = (MDIV + K/65536)  FIN/(PDIV  2SDIV) 
MDIV, PDIV, SDIV for EPLL should conform to these conditions: 
 PDIV: 1  PDIV  63 
 MDIV: 64  MDIV  511 
 SDIV: 0  SDIV  5 
 K: – 32768  K  32767 (K[15:0] is a twos complement integer) 
 Fref (= FIN/PDIV): 2 MHz  Fref  30 MHz 
 FVCO (= (MDIV + K/65536)  FIN/PDIV): 700 MHz  FVCO  1400 MHz 
 FOUT: 22 MHz  FOUT  1400 MHz 
Do not set the value PDIV or MDIV to all zeros. 
SDIV[2:0] controls division ratio of Scaler as described in Table 5-15.
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Exynos 5250_UM 5 Clock Controller 
 5-100  
5.9.1.82 EPLL_CON1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0134, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0=
h=[15:0]=RW=Value of=16-bit DSM (Delta-Sigma Modulator)=0x0=
=
Refer to=5.3.2 Recommended PLL PMS Value for EPLL for more information on recommended K value. 
 
5.9.1.83 EPLL_CON2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0138, Reset Value = 0x0000_0080 
Name Bit Type Description Reset Value 
RSVD [31:13] –=Reserved=0x0=
EXTAFC=x12:8]=RW=Enable pin for FVCO_OUT (Active-high)=0x0=
DCC_ENB=[7]=RW=
Enables Duty Cycle Corrector==
(only for monitoring)=
0 ==Enables DCC=
1 = Disables DCC=
0x1=
AFC_ENB=xS]=RW=
Decides=whether AFC is enabled or not (Active=
low)=
0 ==Enables AFC=
1 = Disables AFC=
0x0=
SSCG_EN=x5]=RW=
Enable pin for dithered mode. (Active high)=
0 = Disables=
1 = Enables=
0x0=
RSVD=x4]=–=Reserved=0x0=
FVCO_EN=x3]=RW=
Enable pin for FVCO_OUT (Active high)=
0 = Disables=
1 = Enables=
0x0=
cSEi=x2]=RW=
Pin pelection for monitoring purposes==
0 = FVCO_OUT is equal to FREc=
1 = FVCO_OUT is equal to FEEa=
0x0=
RSVD=x1:0]=–=Reserved=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-101  
5.9.1.84 VPLL_CON0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0140, Reset Value = 0x0024_0201  
Name Bit Type Description Reset Value 
ENABLE [31] RW 
PLL Enable control 
0 = Disables 
1 = Enables 
0x0 
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL locking indication=
0 = Unlocked=
1 = Locked=
0x0=
RSVD=[28:25]=–=Reserved=0x0=
MDIV=[24:16]=RW=PLL M Divide Value=0x24=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=PLL m=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=PLL S Divide Value=0x1=
=
The reset value of VPLL_CON0 generates 222.75=MHz output clock=for=the input clock frequency of=24=MHz.=
Equation to calculate the=output frequency=is:=
 FOUT = (MDIV + K/65536)  FIN/(PDIV  2SDIV) 
MDIV, PDIV, SDIV for VPLL should conform to these conditions:  
 PDIV: 1  MDIV  63  
 MDIV: 64  MDIV  511 
 SDIV: 0  SDIV  5 
 K: – 32768  K  32767 (K[15:0] is a twos complement integer) 
 Fref (= FIN/PDIV): 2 MHz  Fref  30 MHz 
 FVCO (= (MDIV + K/65536)  FIN/PDIV): 700 MHz  FVCO  1400 MHz 
 FOUT: 22 MHz  FOUT  1400 MHz 
Do not set the value PDIV or MDIV to all zeros. 
Division Ratio of Scaler is controlled by SDIV [2:0] as summarized in Table 5-15. 
Refer to 5.3.3 Recommended PLL PMS Value for VPLL for recommended PMS values.
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Exynos 5250_UM 5 Clock Controller 
 5-102  
5.9.1.85 VPLL_CON1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0144, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0=
SEL_PF=x30:29]=RW=
Value of 2-bit modulation method control=
00 ==Down=spread=
01 ==Up=spread=
1x ==Center=spread=
0x0=
MRo=[28:24]=RW=Value of 5-bit Modulation oate Control=0x0=
MFo=[23:16]=RW=Value of 8-bit Modulation crequency=Control=0x0=
h=[15:0]=RW=Value of 1S-bit Delta Sigma Modulator (DSM)=()=0x0=
=
Modulation Frequency, MF, is=calculated by=the equation:=
 MF = FIN/PDIV/MFR/2^5[Hz] 
Modulation Rate, MR, is calculated by the equation: 
 MR = MFR  MRR/MDIV/2^6  100[%] 
MFR and MRR should conform to these conditions: 
 MFR: 0  MFR  255 
 MRR: 1  MRR  31 
 1  MRR  MFR  512
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Exynos 5250_UM 5 Clock Controller 
 5-103  
5.9.1.86 VPLL_CON2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0148, Reset Value = 0x0000_0080 
Name Bit Type Description Reset Value 
RSVD [31:13] –=Reserved=0x0=
EXTAFC=x12:8]=RW=Enable pin for FVCO_OUT (Active-high)=0x0=
DCC_ENB=[7]=RW=
Enables Duty Cycle Corrector==
(only for monitoring)=
0 ==Enables DCC=
1 = Disables DCC=
0x1=
AFC_ENB=xS]=RW=
Decides=whether AFC is enabled or not=(Active=
low)=
0 = Enables AFC=
1 = Disables AFC=
0x0=
SSCG_EN=x5]=RW=
Enable pin=for dithered mode (Active high)=
0 = Disables=
1 = Enables=
0x0=
RSVD=x4]=–=Reserved=0x0=
FVCO_EN=x3]=RW=
Enable pin for FVCO_OUT (Active high)=
0 = Disables=
1 = Enables=
0x0=
cSEi=x2]=RW=
Pin pelection for monitoring purposes==
0 = FVCO_OUT is equal to FREc=
1 = FVCO_OUT is equal to FEEa=
0x0=
RSVD=x1:0]=–=Reserved=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-104  
5.9.1.87 GPLL_CON0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0150, Reset Value = 0x00C8_0601 
Name Bit Type Description Reset Value 
ENABLE [31] RW 
PLL Enable control 
0 = Disables 
1 = Enables 
0x0 
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL Locking indication=
0 = Unlocks=
1 = Locks=
0x0=
RSVD=x28]=–=Reserved=0x0=
FSEL=[27]=RW=
Monitoring Frequency=Select pin=
0 = FVCO_OUT = FREc=
1 = FVCO_OUT = FVCl=
0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=PLL M Divide value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=PLL P Divide value=0xS=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=PLL S Divide Value=0x1=
The reset value of=dPLL_CON0 generates=450=MHz output clock for the input clock frequency of 24 MHz.=
Equation to calculate the output frequency=is:=
 FOUT = MDIV  FIN/(PDIV  2SDIV) 
MDIV, PDIV, SDIV for GPLL should conform to these conditions: 
 PDIV: 1  PDIV  63 
 MDIV: 64  MDIV  1023 
 SDIV: 0  SDIV  5 
 Fref (= FIN/PDIV): 2 MHz  Fref  12 MHz 
 FVCO (=MDIV  FIN/PDIV): 700 MHz  FVCO  1400 MHz 
 FOUT: 21.9 MHz  FOUT  1400 MHz 
 
Do not set the value of PDIV [5:0] or MDIV [9:0] to all zeros. 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on 
recommended PMS values. 
SDIV[2:0] controls division ratio of Scaler as described in Table 5-15.
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