Samsung Exynos 5 User Manual

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Exynos 5250_UM 7 Interrupt Combiner 
 7-3  
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
INTG4 
MCUIOP [7] MCUIOP_CTIIRQ MCUIOP [6] MCUIOP_PMUIRQ 
MCUISP [5] MCUISP_CTIIRQ MCUISP [4] MCUISP_PMUIRQ 
SYSMMU[19:16] 
[3] SYSMMU_JPEGX[1] 
System MMU [2] SYSMMU_JPEGX[0] 
[1] SYSMMU_ROTATOR[1] 
[0] SYSMMU_ROTATOR[0] 
INTG5 SYSMMU[27:20] 
[7] SYSMMU_3DNR[1] 
System MMU 
[6] SYSMMU_3DNR[0] 
[5] SYSMMU_MCUISP[1] 
[4] SYSMMU_MCUISP[0] 
[3] SYSMMU_SCALERCISP[1] 
[2] SYSMMU_SCALERCISP[0] 
[1] SYSMMU_FDISP[1] 
[0] SYSMMU_FDISP[0] 
INTG6 SYSMMU[35:28] 
[7] SYSMMU_SSS[1] 
System MMU 
[6] SYSMMU_SSS[0] 
[5] SYSMMU_RTIC[1] 
[4] SYSMMU_RTIC[0] 
[3] SYSMMU_MFCR[1] 
[2] SYSMMU_MFCR[0] 
[1] SYSMMU_ARM[1] 
[0] SYSMMU_ARM[0] 
INTG7 SYSMMU[43:36] 
[7] Reserved 
System MMU 
[6] Reserved 
[5] SYSMMU_TV_M0[1] 
[4] SYSMMU_TV_M0[0] 
[3] SYSMMU_MDMA1[1] 
[2] SYSMMU_MDMA1[0] 
[1] SYSMMU_MDMA0[1] 
[0] SYSMMU_MDMA0[0] 
INTG8 
RSVD [7] Reserved – 
SYSMMU[45:44] [6] SYSMMU_MFCL[1] System MMU [5] SYSMMU_MFCL[0] 
RSVD [4] Reserved –  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-4  
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
[3] Reserved 
[2] Reserved 
[1] Reserved 
[0] Reserved 
INTG9 
RSVD [7] Reserved – [6] Reserved 
SYSMMU[47:46] [5] SYSMMU_DIS1[1] System MMU [4] SYSMMU_DIS1[0] 
RSVD 
[3] Reserved 
– [2] Reserved 
[1] Reserved 
[0] Reserved 
INTG10 
SYSMMU[49:48] 
[7] SYSMMU_ISP[1] 
System MMU [6] SYSMMU_ISP[0] 
[5] SYSMMU_DIS0[1] 
[4] SYSMMU_DIS0[0] 
DP1 [3] DP1 DP1 
RSVD 
[2] Reserved 
– [1] Reserved 
[0] Reserved 
INTG11 
SYSMMU[53:52] [7] SYSMMU_DRCISP[1] System MMU [6] SYSMMU_DRCISP[0] 
RSVD 
[5] Reserved 
– [4] Reserved 
[3] Reserved 
[2] Reserved 
SYSMMU[51:50] [1] SYSMMU_ODC[1] System MMU [0] SYSMMU_ODC[0] 
INTG12 RSVD [7:0] Reserved – 
INTG13 
RSVD [7:2] Reserved – 
MDMA1 [1] MDMA1_ABORT MDMA1 
RSVD [0] Reserved – 
INTG14 RSVD [7:0] Reserved – 
INTG15 
RSVD [7:4] Reserved – 
MDMA0 [3] MDMA0_ABORT MDMA0 
RSVD [2:0]] Reserved –  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-5  
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
INTG16 PEREV 
[7] Reserved 
CDREX block 
[6] Reserved 
[5] Reserved 
[4] Reserved 
[3] PEREV_M1_CDREX 
[2] PEREV_M0_CDREX 
[1] PEREV_A1_CDREX 
[0] PEREV_A0_CDREX 
INTG17 
RSVD [7:4] Reserved – 
C2C 
[3] SSCM_PULSE_IRQ_C2CIF[1] 
CDREX block [2] SSCM_PULSE_IRQ_C2CIF[0] 
[1] SSCM_IRQ_C2CIF[1] 
[0] SSCM_IRQ_C2CIF[0] 
INTG18 
DISP1 
[7] DISP1[3] 
DISP1 [6] DISP1[2] 
[5] DISP1[1] 
[4] DISP1[0] 
RSVD 
[3] Reserved 
– [2] Reserved 
[1] Reserved 
[0] Reserved 
INTG19 
CPU [7] CPU_nRAMERRIRQ CPU [6] CPU_nAXIERRIRQ 
RSVD [5] Reserved – 
ISP block [4] INT_COMB_ISP_GIC ISP block 
FSYS block [3] INT_COMB_IOP_GIC FSYS block 
CDREX block [2] CCI_nERRORIRQ CDREX block 
ISP block [1] INT_COMB_ARMISP_GIC ISP block 
FSYS block [0] INT_COMB_ARMIOP_GIC FSYS block 
INTG20 CPU [0] CPU_nIRQ[0] CPU 
INTG21 CPU [1] CPU_nIRQ[1] CPU 
INTG22 CPU 
[7] CPU_nCNTVIRQ[1] 
CPU 
[6] CPU_nCTIIRQ[1] 
[5] CPU_nCNTPSIRQ[1] 
[4] CPU_nPMUIRQ[1] 
[3] CPU_nCNTPNSIRQ[1]  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-6  
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
[2] CPU_PARITYFAILSCU[1] 
[1] CPU_nCNTHPIRQ[1] 
[0] PARITYFAIL[1] 
INTG23 
RSVD 
[7] Reserved 
– [6] Reserved 
[5] Reserved 
MCT_G[1:0] [4] MCT_G1 MCT [3] MCT_G0 
RSVD [2] Reserved – [1] Reserved 
EINT[0] [0] EINT[0] External interrupt 
INTG24 
SYSMMU[57:56] [6] SYSMMU_G2D[1] System MMU [5] SYSMMU_G2D[0] 
RSVD [4:3] Reserved – 
SYSMMU[55:54] [2] SYSMMU_FIMC_LITE1[1] System MMU [1] SYSMMU_FIMC_LITE1[0] 
EINT[1] [0] EINT[1] External interrupt 
INTG25 
MCT_G[3:2] [3] MCT_G3 MCT [2] MCT_G2 
EINT[3:2] [1] EINT[3] External interrupt [0] EINT[2] 
INTG26 EINT[5:4] [1] EINT[5] External interrupt [0] EINT[4] 
INTG27 EINT[7:6] [1] EINT[7] External interrupt [0] EINT[6] 
INTG28 EINT[9:8] [1] EINT[9] External interrupt [0] EINT[8] 
INTG29 EINT[11:10] [1] EINT[11] External interrupt [0] EINT[10] 
INTG30 EINT[13:12] [1] EINT[13] External interrupt [0] EINT[12] 
INTG31 EINT[15:14] [1] EINT[15] External interrupt [0] EINT[14] 
  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-7  
7.4 Functional Description 
An interrupt enable bit controls an interrupt source in an interrupt group. IESRn registers and IECRn registers 
control the interrupt enable bits. IESRn register can toggle an interrupt bit to 1. If you write 1 to a bit position on 
IESRn, the corresponding bit on the interrupt enable bits are set to 1. Alternatively, IECRn register can toggle an 
interrupt enable bit to 0. If you write 1 to a bit position on IECRn, the corresponding bit on the interrupt enable 
bits is cleared to 0. This feature eases the addressing of resource sharing issues in a multi-processor system. 
There are several interrupt sources in an interrupt group. If an interrupt enable bit is 0, the corresponding 
interrupt is masked. All the interrupt sources in an interrupt group including masked interrupt sources are ORed to 
form a combined interrupt request signal. This combined group interrupt request output signal is connected to an 
input of a GIC. 
ISTRn register reads each interrupt source status before an interrupt enable-bit masks it. The combined group 
interrupt request output signal can be shown by reading CIPSR0 register. 
 
  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-8  
7.5 Register Description 
7.5.1 Register Map Summary 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
Register Offset Description Reset Value 
IESR0 0x0000 Interrupt enable set register for group 0 to 3 0x00000000 
IECR0 0x0004 Interrupt enable clear register for group 0 to 3 0x00000000 
ISTR0 0x0008 Interrupt status register for group 0 to 3 Undefined 
IMSR0 0x000C Interrupt masked status register for group 0 to 3 Undefined 
IESR1 0x0010 Interrupt enable set register for group 4 to 7 0x00000000 
IECR1 0x0014 Interrupt enable clear register for group 4 to 7 0x00000000 
ISTR1 0x0018 Interrupt status register for group 4 to 7 Undefined 
IMSR1 0x001C Interrupt masked status register for group 4 to 7 Undefined 
IESR2 0x0020 Interrupt enable set register for group 8 to 11 0x00000000 
IECR2 0x0024 Interrupt enable clear register for group 8 to 11 0x00000000 
ISTR2 0x0028 Interrupt status register for group 8 to 11 Undefined 
IMSR2 0x002C Interrupt masked status register for group 8 to 11 Undefined 
IESR3 0x0030 Interrupt enable set register for group 12 to 15 0x00000000 
IECR3 0x0034 Interrupt enable clear register for group 12 to 15 0x00000000 
ISTR3 0x0038 Interrupt masked status register for group 12 to 15 Undefined 
IMSR3 0x003C Interrupt status register for group 12 to 15 Undefined 
IESR4 0x0040 Interrupt enable set register for group 16 to 19 0x00000000 
IECR4 0x0044 Interrupt enable clear register for group 16 to 19 0x00000000 
ISTR4 0x0048 Interrupt status register for group 16 to 19 Undefined 
IMSR4 0x004C Interrupt masked status register for group 16 to 19 Undefined 
IESR5 0x0050 Interrupt enable set register for group 20 to 23 0x00000101 
IECR5 0x0054 Interrupt enable clear register for group 20 to 23 0x00000101 
ISTR5 0x0058 Interrupt status register for group 20 to 23 Undefined 
IMSR5 0x005C Interrupt masked status register for group 20 to 23 Undefined 
IESR6 0x0060 Interrupt enable set register for group 24 to 27 0x00000000 
IECR6 0x0064 Interrupt enable clear register for group 24 to 27 0x00000000 
ISTR6 0x0068 Interrupt status register for group 24 to 27 Undefined 
IMSR6 0x006C Interrupt masked status register for group 24 to 27 Undefined 
IESR7 0x0070 Interrupt enable set register for group 28 to 31 0x00000000 
IECR7 0x0074 Interrupt enable clear register for group 28 to 31 0x00000000 
ISTR7 0x0078 Interrupt masked status register for group 28 to 31 Undefined 
IMSR7 0x007C Interrupt status register for group 28 to 31 Undefined 
CIPSR0 0x0100 Combined interrupt pending status 0 Undefined  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-9  
7.5.1.1 IESR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
SYSMMU_SCALERPISP[1] [31] RW Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the 
interrupt request is served. 
Write 
0 = Does not change the current setting  
1 = Sets the interrupt enable bit to 1. 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
SYSMMU_SCALERPISP[0] [30] RW 0 
SYSMMU_FIMC_LITE0[1] [29] RW 0 
SYSMMU_FIMC_LITE0[0] [28] RW 0 
SYSMMU_DISP1_M0[1] [27] RW 0 
SYSMMU_DISP1_M0[0] [26] RW 0 
SYSMMU_FIMC_LITE2[1] [25] RW 0 
SYSMMU_FIMC_LITE2[0] [24] RW 0 
SYSMMU_GSCL3[1] [25] RW Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the 
interrupt request is served. 
Write 
0 = Does not change the current setting 
1 = Sets the interrupt enable bit to 1 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
SYSMMU_GSCL3[0] [24] RW 0 
SYSMMU_GSCL2[1] [23] RW 0 
SYSMMU_GSCL2[0] [20] RW 0 
SYSMMU_GSCL1[1] [19] RW 0 
SYSMMU_GSCL1[0] [18] RW 0 
SYSMMU_GSCL0[1] [17] RW 0 
SYSMMU_GSCL0[0] [16] RW 0 
CPU_nCNTVIRQ[0] [15] RW Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the 
interrupt request is served. 
Write 
0 = Does not change the current setting 
1 = Sets the interrupt enable bit to 1 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
CPU_nCNTPSIRQ[0] [14] RW 0 
CPU_nCNTPSNIRQ[0] [13] RW 0 
CPU_nCNTHPIRQ[0] [12] RW 0 
CPU_nCTIIRQ[0] [11] RW 0 
CPU_nPMUIRQ[0] [10] RW 0 
CPU_PARITYFAILSCU[0] [9] RW 0 
CPU_PARITYFAIL0 [8] RW 0 
TZASC_XR1BXW [7] RW Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the 
interrupt request is served. 
Write 
0 = Does not change the current setting 
1 = Sets the interrupt enable bit to 1 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
TZASC_XR1BXR [6] RW 0 
TZASC_XLBXW [5] RW 0 
TZASC_XLBXR [4] RW 0 
TZASC_DRBXW [3] RW 0 
TZASC_DRBXR [2] RW 0 
TZASC_CBXW [1] RW 0 
TZASC_CBXR [0] RW 0 
  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-10  
7.5.1.2 IECR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0004, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
SYSMMU_SCALERPISP[1] [31] RW Clears the corresponding interrupt enable bit to 
0.  
If the interrupt enable bit is cleared, the interrupt 
is masked. 
Write 
0 = Does not change the current setting 
1 = Clears the interrupt enable bit to 0 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
SYSMMU_SCALERPISP[0] [30] RW 0 
SYSMMU_FIMC_LITE0[1] [29] RW 0 
SYSMMU_FIMC_LITE0[0] [28] RW 0 
SYSMMU_DISP1_M0[1] [27] RW 0 
SYSMMU_DISP1_M0[0] [26] RW 0 
SYSMMU_FIMC_LITE2[1] [25] RW 0 
SYSMMU_FIMC_LITE2[0] [24] RW 0 
SYSMMU_GSCL3[1] [25] RW Clear the corresponding interrupt enable bit to 
0.  
If the interrupt enable bit is cleared, the interrupt 
is masked. 
Write 
0 = Does not change the current setting 
1 = Clears the interrupt enable bit to 0. 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
SYSMMU_GSCL3[0] [24] RW 0 
SYSMMU_GSCL2[1] [23] RW 0 
SYSMMU_GSCL2[0] [20] RW 0 
SYSMMU_GSCL1[1] [19] RW 0 
SYSMMU_GSCL1[0] [18] RW 0 
SYSMMU_GSCL0[1] [17] RW 0 
SYSMMU_GSCL0[0] [16] RW 0 
CPU_nCNTVIRQ[0] [15] RW Clear the corresponding interrupt enable bit to 
0.  
If the interrupt enable bit is cleared, the interrupt 
is masked. 
Write 
0 = Does not change the current setting 
1 = Clears the interrupt enable bit to 0. 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
CPU_nCNTPSIRQ[0] [14] RW 0 
CPU_nCNTPSNIRQ[0] [13] RW 0 
CPU_nCNTHPIRQ[0] [12] RW 0 
CPU_nCTIIRQ[0] [11] RW 0 
CPU_nPMUIRQ[0] [10] RW 0 
CPU_PARITYFAILSCU[0] [9] RW 0 
CPU_PARITYFAIL0 [8] RW 0 
TZASC_XR1BXW [7] RW Clear the corresponding interrupt enable bit to 
0.  
If the interrupt enable bit is cleared, the interrupt 
is masked. 
Write 
0 = Does not change the current setting 
1 = Clears the interrupt enable bit to 0. 
Read 
The current interrupt enable bit 
0 = Masks 
0 
TZASC_XR1BXR [6] RW 0 
TZASC_XLBXW [5] RW 0 
TZASC_XLBXR [4] RW 0 
TZASC_DRBXW [3] RW 0 
TZASC_DRBXR [2] RW 0 
TZASC_CBXW [1] RW 0 
TZASC_CBXR [0] RW 0  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-11  
Name Bit Type Description Reset Value 
1 = Enables 
  
						

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Exynos 5250_UM 7 Interrupt Combiner 
 7-12  
7.5.1.3 ISTR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0008, Reset Value = Undefined 
Name Bit Type Description Reset Value 
SYSMMU_SCALERPISP[1] [31] R 
Interrupt pending status  
The corresponding interrupt enable bit does not 
affect this pending status. 
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
SYSMMU_SCALEoPISP[0]=[30]=o=–=
SYSMMU_FIMC_LITE0[1]=[29]=o=–=
SYSMMU_FIMC_LITE0[0]=[28]=o=–=
SYSMMU_DISP1_M0[1]=[27]=o=–=
SYSMMU_DISP1_M0[0]=[26]=o=–=
SYSMMU_FIMC_LITE2[1]=[25]=o=–=
SYSMMU_FIMC_LITE2[0]=[24]=o=–=
SYSMMU_GSCL3[1]=[25]=o=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
SYSMMU_GSCL3[0]=[24]=o=–=
SYSMMU_GSCL2[1]=[23]=o=–=
SYSMMU_GSCL2[0]=[20]=o=–=
SYSMMU_GSCL1[1]=[19]=o=–=
SYSMMU_GSCL1[0]=[18]=o=–=
SYSMMU_GSCL0[1]=[17]=o=–=
SYSMMU_GSCL0[0]=[16]=o=–=
CPU_nCNTVIRQ[0]=[15]=o=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
CPU_nCNTPSIRQ[0]=[14]=o=–=
CPU_nCNTPSNIRQ[0]=[13]=o=–=
CPU_nCNTHPIRQ[0]=[12]=o=–=
CPU_nCTIIRQ[0]=[11]=o=–=
CPU_nPMUIRQ[0]=[10]=o=–=
CPU_PARITYFAILSCU[0]=[9]=o=–=
CPU_PARITYFAIL0=[8]=o=–=
TZASC_XR1BXt=[7]=o=
Interrupt pending status==
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
TZASC_XR1BXo=[6]=o=–=
TZASC_XLBXW=[5]=o=–=
TZASC_XLBXR=[4]=o=–=
TZASC_DRBXW=[3]=o=–=
TZASC_DRBXR=[2]=o=–=
TZASC_CBXt=[1]=o=–=
TZASC_CBXo=[0]=o=–=
=