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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-28  
  FUARTCLK = baudrate  16 
 
 This allows sufficient time to write the received data to the receive FIFO.
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-29  
12.6.1.13 UINTPn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0030, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0=
MODEM=[3]=RW=Generates Modem interrupt=0=
TXa=[2]=RW=Generates Transmit interrupt=0=
ERROo=[1]=RW=Generates Error interrupt=0=
RXa=[0]=RW=Generates Receive interrupt=0=
=
Interrupt pending contains information of the interrupts that are generated.=
If=one of=these=4 bits is logical high (1), each UART channel generates=interrupt.=
This must be cleared in the interrupt service routine after clearing interrupt pending in Interrupt Controller (INTC).=
Clear specific=bits of UINTP by writing=1=to the bits that you want to clear.=
=
12.6.1.14 UINTSn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0034, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0=
MODEM=[3]=o=Generates Modem interrupt=0=
TXa=[2]=o=Generates Transmit interrupt=0=
ERROo=[1]=o=Generates Error interrupt=0=
RXa=[0]=o=Generates Receive interrupt=0=
=
Interrupt Source contains information of the=interrupt that=are generated,=regardless of the value of Interrupt Mask.=
=
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-30  
12.6.1.15 UINTMn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0038, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0=
MODEM=[3]=RW=Mask Modem interrupt=0=
TXa=[2]=RW=Mask Transmit interrupt=0=
ERROo=[1]=RW=Mask Error interrupt=0=
RXa=[0]=RW=Mask Receive interrupt=0=
=
Figure 12-10 illustrates the block diagram of UNITS, UINTP and UINTM. 
 
  
    Figure 12-10   Block Diagram of UINTS, UINTP and UINTM 
Interrupt Mask contains information about the interrupt source that is masked. When a specific bit is set to 1, 
interrupt request signal to the Interrupt Controller is not generated even though corresponding Interrupt Source is 
generated.  
NOTE: If the Mask bit is 0, the interrupt requests are serviced from the corresponding Interrupt Source. 
 
 
 UART_INT (UART interrupt)UINTS
UINTPUINTM
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-1  
13 IIC-Bus Interface 
13.1 Overview 
The Exynos 5250 RISC microprocessor supports four multi-master I2C-bus serial interfaces. To transmit 
information between bus masters and peripheral devices connected to the I2C-bus, a dedicated Serial Data Line 
(SDA) and a Serial Clock Line (SCL) is used. Both SDA and SCL lines are bi-directional. 
In multi-master I2C-bus mode, multiple Exynos 5250 RISC microprocessors receive or transmit serial data to or 
from slave devices. The master Exynos 5250 initiates and terminates a data transfer through the I2C-bus. The I2C-
bus in the Exynos 5250 uses a standard bus arbitration procedure. 
To control multi-master I2C-bus operations, values must be written to the following registers: 
 Multi-master I2C-bus control register-I2CCON 
 Multi-master I2C-bus control/status register-I2CSTAT 
 Multi-master I2C-bus Tx/Rx data shift register-I2CDS 
 Multi-master I2C-bus address register-I2CADD 
When the I2C-bus is free, both SDA and SCL lines should be at High level. A High-to-Low transition of SDA 
initiates a Start condition. A Low-to-High transition of SDA initiates a Stop condition, while SCL remains steady at 
High Level. 
The master device always generates Start and Stop conditions. First 7-bit address value in the data byte that is 
transferred through SDA line after the Start condition has been initiated, can determine the slave device, which the 
bus master device has selected. The 8th bit determines the direction of the transfer (Read or Write). 
Every data byte that is transmitted to the SDA line should be eight bits in total. There is no limit to send or receive 
bytes during the Bus Transfer operation. Data is always sent from Most-Significant Bit (MSB) first, and every byte 
should be immediately followed by an acknowledgement (ACK) bit.
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-2  
Figure 13-1 illustrates the I2C-bus block diagram. 
 
    Figure 13-1   I2C-Bus Block Diagram 
 
 
 PCLK
Address Register
SDA4-bit Prescaler
I2C-Bus Control Logic
I2CSTATI2CCON
Comparator
Shift Register
Shift Register(I2CDS)
Data Bus
SCL
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-3  
13.2 Features 
 9-channels Multi-Master, Slave I2C-bus interfaces   
(8-channels for general purpose, 1-channel for HDMI dedicated) 
 7-bit addressing mode 
 Serial, 8-bit oriented, and bi-directional data transfer 
 Supports up to 100 kbit/s in the Standard Mode  
 Supports up to 400 kbit/s in the Fast Mode 
 Supports Master Transmit, Master Receive, Slave Transmit and Slave Receive operation 
 Supports Interrupt or Polling events
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-4  
13.3 IIC-Bus Interface Operation  
The Exynos 5250 I2C-bus interface has four operation modes:  
 Master Transmitter Mode 
 Master Receive Mode 
 Slave Transmitter Mode 
 Slave Receive Mode 
The functional relationships among these operating modes are described in this section.  
 
13.3.1 Start and Stop Conditions 
When the I2C-bus interface is inactive, it is usually in Slave Mode. In other words, the interface should be in Slave 
Mode before detecting a Start condition on the SDA line (a Start condition is initiated with a High-to-Low transition 
of the SDA line while the clock signal of SCL is High). When the interface state is changed to Master mode, SDA 
line initiates data transfer and generates SCL signal. 
A Start condition transfers one-byte serial data through SDA line, and a Stop condition terminates the data 
transfer. A Stop condition is a Low-to-High transition of the SDA line while SCL is High. The master generates 
Start and Stop conditions. The I2C-bus becomes busy when a Start condition is generated. On the other hand, a 
Stop condition makes the I2C-bus free.  
When a master initiates a Start condition, it should send a slave address to notify the slave device. One byte of 
address field consists of a 7-bit address and a 1-bit transfer direction indicator (that shows Write or Read).  
When bit 8 is 0, it indicates a Write operation (Transmit Operation); when bit 8 is 1, it indicates a request for Data 
Read (Receive Operation). 
The master transmits Stop condition to complete the transfer operation. W hen the master wants to continue the 
data transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the 
Read-Write operation is performed in multiple formats. 
Figure 13-2 illustrates the Start and Stop condition. 
 
    Figure 13-2   Start and Stop Condition SCL
SDASDA
SCL
Start
Condition
Stop
Condition
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-5  
13.3.2 Data Transfer Format 
Every byte placed on the SDA line should be 8 bits in length. There is no limit to transmit bytes per transfer. The 
first byte that follows a Start condition should contain the address field. W hen the I2C-bus is operating in Master 
Mode, the master transmits the address field. Each byte should be followed by an acknowledgement (ACK) bit. 
The MSB bit of the serial data and addresses are sent first.  
Figure 13-3 illustrates the I2C-bus Interface Data Format. 
 
    Figure 13-3   I2C-Bus Interface Data Format 
Figure 13-4 illustrates the data transfer on the I2C-bus. 
 
    Figure 13-4   Data Transfer on the I2C-Bus SDA
Acknowledgement
Signal from Receiver
SCL
S
12789129
Acknowledgement
Signal from ReceiverMSB
ACK
Byte Complete, Interrupt
within Receiver
Clock Line Held Low by
receiver and/or transmitter
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-6  
13.3.3 ACK Signal Transmission 
To complete a one-byte transfer operation, the receiver sends an ACK bit to the transmitter. The ACK pulse 
occurs at the ninth clock of the SCL line. Eight clocks are required for the 1-byte data transfer. The master 
generates clock pulse that is required to transmit the ACK bit. 
The transmitter sets the SDA line to High to release the SDA line when the ACK clock pulse is received. The 
receiver drives the SDA line Low during the ACK clock pulse so that, the SDA keeps Low during the High period 
of the ninth SCL pulse. The software (I2CSTAT) enables or disables ACK bit transmit function. However, the ACK 
pulse on the ninth clock of SCL is required to complete the 1-byte data transfer operation. 
Figure 13-5 illustrates the acknowledgement on the I2C-bus. 
 
    Figure 13-5   Acknowledgement on the I2C-Bus 
  
Data Output by
Transmitter
Data Output by
Receiver
SCL from
Master
Start
Condition
Clock Pulse for Acknowledgment
Clock to Output
987S12
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Exynos 5250_UM 13 IIC-Bus Interface 
 13-7  
13.3.4 Read-Write Operation 
When data is transmitted in Transmitter Mode, the I2C-bus interface waits until I2C-bus Data Shift (I2CDS) register 
receives the new data. Before the new data is written to the register, the SCL line is held Low. The line is released 
only after the data has been written. Exynos 5250 holds the interrupt to identify the completion of current data 
transfer. After the CPU receives the interrupt request, it writes new data to the I2CDS register again. 
When data is received in Receive Mode, the I2C-bus interface waits until I2CDS register is read. Before the new 
data is read out, the SCL line is held Low. The line is released only after the data has been read. Exynos 5250 
holds the interrupt to identify the completion of new data reception. After the CPU receives the interrupt request, it 
reads the data from the I2CDS register. 
 
13.3.5 Bus Arbitration Procedures 
Arbitration occurs on the SDA line to prevent the contention on the bus between two masters. When a master with 
a SDA High level, detects other master with a SDA active Low level, it does not initiate a data transfer because 
the current level on the bus, does not correspond to its own. The arbitration procedure extends until the SDA line 
turns High. 
When the masters lower the SDA line, simultaneously each master evaluates whether the mastership is allocated 
by itself or not. For the purpose of evaluation, each master detects the address bits. While each master generates 
the slave address, it detects the address bit on the SDA line because the SDA line is likely to become Low than 
High.  
In a situation where one master generates a Low as first address bit, while the other master is maintaining High. In 
this case, both masters detect Low on the bus, because the Low status is superior to the High status in power. 
When this happens, Low (as the first bit of address) generating master gets the mastership while High (as the first 
bit of address) generating master withdraws the mastership. When both masters generate Low as the first bit of 
address, there is arbitration for the second address bit again. This arbitration continues till the end of last address 
bit.  
 
13.3.6 Abort Conditions 
When a slave receiver cannot acknowledge the confirmation of the slave address, it holds the level of the SDA 
line as High. In this case, the master generates a Stop condition and cancels the transfer. 
When a master receiver is involved in the aborted transfer, it signals the end of slave transmit operation by 
canceling the generation of an ACK. It performs this after the last data byte was received from the slave. The 
slave transmitter releases the SDA to allow a master to generate a Stop condition. 
 
13.3.7 Configuring IIC-Bus 
To control the frequency of the Serial Clock (SCL), the 4-bit prescaler value is programmed in the I2CCON 
register. The I2C-bus interface address is stored in the I2C-bus address (I2CADD) register (by default, the I2C-bus 
interface address has an unknown value).
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