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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-237  
4.4.1.333 EXT_INT20_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0830, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0000=
FLTEN7[1]=[15]=RW=
Enables Filter for EXT_INT20[1]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH7[1]=[14:8]=RW=Filtering width of EXT_INT20[1]=0x00=
FLTEN7[0]=[7]=RW=
Enables Filter=for EXT_INT20[0]=
0x0 ==Disables=
0x1 = Enables=
0x0=
FLTWIDTH7[0]=[6:0]=RW=Filtering width of EXT_INT20[0]=0x00=
=
4.4.1.334 EXT_INT20_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0834, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-238  
4.4.1.335 EXT_INT21_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0838, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN8[3] [31] RW 
Enables Filter for EXT_INT21[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[3] [30:24] RW Filtering width of EXT_INT21[3] 0x00 
FLTEN8[2] [23] RW 
Enables Filter for EXT_INT21[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[2] [22:16] RW Filtering width of EXT_INT21[2] 0x00 
FLTEN8[1] [15] RW 
Enables Filter for EXT_INT21[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[1] [14:8] RW Filtering width of EXT_INT21[1] 0x00 
FLTEN8[0] [7] RW 
Enables Filter for EXT_INT21[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[0] [6:0] RW Filtering width of EXT_INT21[0] 0x00 
 
4.4.1.336 EXT_INT21_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x083C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-239  
4.4.1.337 EXT_INT22_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0840, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN9[3] [31] RW 
Enables Filter for EXT_INT22[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[3] [30:24] RW Filtering width of EXT_INT22[3] 0x00 
FLTEN9[2] [23] RW 
Enables Filter for EXT_INT22[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[2] [22:16] RW Filtering width of EXT_INT22[2] 0x00 
FLTEN9[1] [15] RW 
Enables Filter for EXT_INT22[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[1] [14:8] RW Filtering width of EXT_INT22[1] 0x00 
FLTEN9[0] [7] RW 
Enables Filter for EXT_INT22[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[0] [6:0] RW Filtering width of EXT_INT22[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-240  
4.4.1.338 EXT_INT22_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0844, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN9[7] [31] RW 
Enables Filter for EXT_INT22[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[7] [30:24] RW Filtering width of EXT_INT22[7] 0x00 
FLTEN9[6] [23] RW 
Enables Filter for EXT_INT22[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[6] [22:16] RW Filtering width of EXT_INT22[6] 0x00 
FLTEN9[5] [15] RW 
Enables Filter for EXT_INT22[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[5] [14:8] RW Filtering width of EXT_INT22[5] 0x00 
FLTEN9[4] [7] RW 
Enables Filter for EXT_INT22[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[4] [6:0] RW Filtering width of EXT_INT22[4] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-241  
4.4.1.339 EXT_INT14_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0900, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT14=
_MASK[7]=[7]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT14=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masked=0x1=
EXT_INT14=
_MASK[5]=[5]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT14=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT14=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT14=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT14=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT14=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-242  
4.4.1.340 EXT_INT15_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0904, Reset Value = 0x0000_0003 
Name Bit Type Description Reset Value 
RSVD [31:2] –=Reserved=0x00000000=
EXT_INT15=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT15=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
4.4.1.341 EXT_INT16_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0908, Reset Value = 0x0000_000F 
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0x0000000=
EXT_INT1S=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT1S=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT1S=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT1S=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
4.4.1.342 EXT_INT17_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x090C, Reset Value = 0x0000_000F 
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0x0000000=
EXT_INT17=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT17=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT17=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT17=
_MASK[0]=[0]=RW=0x0 ==Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
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Exynos 5250_UM 4 Pad Control 
 4-243  
4.4.1.343 EXT_INT18_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0910, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT18=
_MASK[7]=[7]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT18=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT18=
_MASK[5]=[5]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT18=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT18=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT18=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT18=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT18=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-244  
4.4.1.344 EXT_INT19_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0914, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT19=
_MASK[7]=[7]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT19=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT19=
_MASK[5]=[5]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT19=
_MASK[4]=[4]=RW=0x0 = Enable=Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT19=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT19=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT19=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT19=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-245  
4.4.1.345 EXT_INT20_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0918, Reset Value = 0x0000_0003 
Name Bit Type Description Reset Value 
RSVD [31:2] –=Reserved=0x00000000=
EXT_INT20=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT20=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
4.4.1.346 EXT_INT21_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x091C, Reset Value = 0x0000_000F 
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0x0000000=
EXT_INT21=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT21=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT21=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT21=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-246  
4.4.1.347 EXT_INT22_MASK 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0920, Reset Value = 0x0000_00FF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
EXT_INT22=
_MASK[7]=[7]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT22=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT22=
_MASK[5]=[5]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT22=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT22=
_MASK[3]=[3]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT22=
_MASK[2]=[2]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT22=
_MASK[1]=[1]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT22=
_MASK[0]=[0]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
=
=
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