Samsung Exynos 5 User Manual

							 
      
List of Figures 
Figure Title Page 
Number  Number 
 
Figure 1-1      Block Diagram of Exynos 5250 ......................................................................................................... 1-5 
 
Figure 4-1      GPIO Block Diagram ........................................................................................................................ 4-4 
 
Figure 5-1      Exynos 5250 Clock Domains ............................................................................................................ 5-2 
Figure 5-2      Exynos 5250 Clock Generation Circuit (CPU, BUS, DRAM Clocks) 1 ........................................... 5-14 
Figure 5-3      Exynos 5250 Clock Generation Circuit (CPU, BUS, DRAM Clocks) 2 ........................................... 5-15 
Figure 5-4      Exynos 5250 Clock Generation Circuit (Special Clocks) 1 ............................................................. 5-16 
Figure 5-5      Exynos 5250 Clock Generation Circuit (Special Clocks) 2 ............................................................. 5-17 
Figure 5-6      Exynos 5250 CLKOUT Control Logic ............................................................................................. 5-28 
Figure 5-7      Exynos 5250 Clock Controller Address Map .................................................................................. 5-33 
 
Figure 6-1      Interrupt Sources Connection ........................................................................................................... 6-2 
 
Figure 8-1      Two type of DMA Controller .............................................................................................................. 8-1 
 
Figure 9-1      Block Diagram of SROM Controller Introduction .............................................................................. 9-1 
Figure 9-2      SROM Controller nWAIT Timing Diagram ........................................................................................ 9-2 
Figure 9-3      SROM Controller Read Timing Diagram .......................................................................................... 9-3 
Figure 9-4      SROM Controller Page Read Timing Diagram ................................................................................. 9-3 
Figure 9-5      SROM Controller Write Timing Diagram .......................................................................................... 9-4 
 
Figure 10-1      PW M Cycle ................................................................................................................................... 10-2 
Figure 10-2      PW M TIMER Clock Tree Diagram ................................................................................................ 10-3 
Figure 10-3      Timer Operations .......................................................................................................................... 10-5 
Figure 10-4      Double Buffering ........................................................................................................................... 10-7 
Figure 10-5      Timer Operation ............................................................................................................................ 10-8 
Figure 10-6      PW M ............................................................................................................................................. 10-9 
Figure 10-7      Inverter On/Off ............................................................................................................................ 10-10 
Figure 10-8      Waveform when a Dead Zone Feature is Enabled..................................................................... 10-11 
 
Figure 11-1      Watchdog Timer Block Diagram ................................................................................................... 11-2 
 
Figure 12-1      Block Diagram of UART ................................................................................................................ 12-2 
Figure 12-2      UART AFC Interface ..................................................................................................................... 12-4 
Figure 12-3      UART Receives the Five Characters Including Two Errors ......................................................... 12-7 
Figure 12-4      IrDA Function Block Diagram ....................................................................................................... 12-8 
Figure 12-5      Serial I/O Frame Timing Diagram (Normal UART) ....................................................................... 12-8 
Figure 12-6      Infra-Red Transmit Mode Frame Timing Diagram ........................................................................ 12-9 
Figure 12-7      Infra-Red Receive Mode Frame Timing Diagram ......................................................................... 12-9 
Figure 12-8      Input Clock Diagram for UART ................................................................................................... 12-10 
Figure 12-9      nCTS and Delta CTS Timing Diagram ....................................................................................... 12-25 
Figure 12-10      Block Diagram of UINTS, UINTP and UINTM .......................................................................... 12-30 
 
 
  
						

							 
      
Figure 13-1      I2C-Bus Block Diagram ................................................................................................................. 13-2 
Figure 13-2      Start and Stop Condition ............................................................................................................... 13-4 
Figure 13-3      I2C-Bus Interface Data Format ..................................................................................................... 13-5 
Figure 13-4      Data Transfer on the I2C-Bus ....................................................................................................... 13-5 
Figure 13-5      Acknowledgement on the I2C-Bus ................................................................................................ 13-6 
Figure 13-6      Operations in Master/Transmitter Mode ....................................................................................... 13-8 
Figure 13-7      Operations in Master/Receiver Mode ......................................................................................... 13-10 
Figure 13-8      Operations in Slave/Transmitter Mode ....................................................................................... 13-11 
Figure 13-9      Operations in Slave/Receiver Mode ........................................................................................... 13-12 
 
Figure 14-1      SPI Transfer Format ..................................................................................................................... 14-5 
Figure 14-2      Input Clock Diagram for SPI ......................................................................................................... 14-6 
Figure 14-3      Auto Chip Select Mode W aveform (CPOL = 0, CPHA = 0, CH_W IDTH = Byte) ....................... 14-12 
 
Figure 15-1      Block Diagram of Display Controller ............................................................................................. 15-1 
Figure 15-2      Block Diagram of the Data Flow ................................................................................................... 15-5 
Figure 15-3      Block Diagram of the Interface ..................................................................................................... 15-6 
Figure 15-4      16-bpp (5:6:5) Display Types...................................................................................................... 15-21 
Figure 15-5      Blending Equation ....................................................................................................................... 15-28 
Figure 15-6      Blending Diagram ....................................................................................................................... 15-29 
Figure 15-7      Blending Factor Decision ............................................................................................................ 15-30 
Figure 15-8      Blending Factor Decision ............................................................................................................ 15-31 
Figure 15-9      Timing Diagram for LR_MERGER Block .................................................................................... 15-32 
Figure 15-10      Timing Diagram for LR_MERGER Block .................................................................................. 15-33 
Figure 15-11      Output Frame for LR_MERGER Block ..................................................................................... 15-34 
Figure 15-12      Color Key Function Configurations ........................................................................................... 15-35 
Figure 15-13      Blending and Color-Key Function ............................................................................................. 15-36 
Figure 15-14      Blending Decision Diagram ...................................................................................................... 15-37 
Figure 15-15      Image Enhancement Flow ........................................................................................................ 15-38 
Figure 15-19      Scrolling in Virtual Display ........................................................................................................ 15-44 
Figure 15-20      RGB Interface Timing ............................................................................................................... 15-45 
Figure 15-21      RGB Interface Timing (RGB Parallel) ....................................................................................... 15-46 
Figure 15-27      Indirect i80 System Interface WRITE Cycle Timing .................................................................. 15-48 
 
Figure 16-1      ADC Functional Block Diagram .................................................................................................... 16-2 
Figure 16-2      Input Clock Diagram for ADC ....................................................................................................... 16-4 
 
 
  
						

							 
      
List of Tables 
Table Title Page 
Number  Number 
 
Table 5-1      Operating Frequencies in Exynos 5250 ............................................................................................. 5-3 
Table 5-2      APLL, MPLL, BPLL, CPLL and GPLL PMS Value ........................................................................... 5-10 
Table 5-3      EPLL PMS Value ............................................................................................................................. 5-11 
Table 5-4      VPLL PMS Value ............................................................................................................................. 5-12 
Table 5-5      Maximum Input Frequency for Clock Divider-1 ................................................................................ 5-18 
Table 5-6      Maximum Input Frequency for Clock Divider-2 ................................................................................ 5-19 
Table 5-7      Maximum Input Frequency for Clock Divider-3 ................................................................................ 5-20 
Table 5-8      Maximum Input Frequency for Clock Divider-4 ................................................................................ 5-21 
Table 5-9      Maximum Input Frequency for Clock Divider-5 ................................................................................ 5-22 
Table 5-10      Maximum Input Frequency for Clock Divider-6 .............................................................................. 5-22 
Table 5-11      Special Clocks in Exynos 5250 ...................................................................................................... 5-26 
Table 5-12      I/O Clocks in Exynos 5250 ............................................................................................................. 5-27 
Table 5-13      CLKOUT Input Clock Selection Information (Part 1) ..................................................................... 5-29 
Table 5-14      CLKOUT Input Clock Selection Information (Part 2) ..................................................................... 5-30 
Table 5-15      Division Ratio of Scaler .................................................................................................................. 5-50 
 
Table 6-1      GIC Configuration Values .................................................................................................................. 6-1 
Table 6-2      External GIC Interrupt Table (SPI[127:32]: Non-Combined Interrupt) ............................................... 6-3 
Table 6-3      External GIC Interrupt Table (SPI[31:0]: Combined Interrupt) ........................................................... 6-6 
Table 6-4      External GIC Interrupt Table (PPI[15:0]) .......................................................................................... 6-12 
 
Table 7-1      Interrupt Groups of Interrupt Combiner .............................................................................................. 7-2 
 
Table 8-1      DMA Request Mapping Table ............................................................................................................ 8-2 
 
Table 10-1      Minimum and Maximum Resolution based on Prescaler and Clock Divider Values ..................... 10-5 
 
Table 12-1      Interrupts in Connection with FIFO ................................................................................................ 12-6 
 
Table 15-1      Features of the Display Controller ................................................................................................. 15-2 
Table 15-2      32-bpp (8:8:8:8) Palette Data Format .......................................................................................... 15-24 
Table 15-3      25-bpp (A: 8:8:8) Palette Data Format ......................................................................................... 15-24 
Table 15-4      19-bpp (A: 6:6:6) Palette Data Format ......................................................................................... 15-25 
Table 15-5      16-bpp (A: 5:5:5) Palette Data Format ......................................................................................... 15-25 
Table 15-6      Relation 16-bpp between VCLK and CLKVAL (TFT, Frequency of Video Clock Source = 300 MHz) .. 
  .................................................................................................................................................. 15-40 
Table 15-7      i80 Output Mode .......................................................................................................................... 15-43 
Table 15-8      RGB I/F Signal Description .......................................................................................................... 15-45 
 
  
						

							 
      
List of Conventions 
Register RW Access Type Conventions 
Type Definition Description 
R Read Only The application has permission to read the Register field. Writes to read-only fields 
have no effect. 
W Write Only The application has permission to write in the Register field. 
RW Read & Write The application has permission to read and writes in the Register field. The 
application sets this field by writing 1’b1 and clears it by writing 1’b0. 
 
Register Value Conventions 
Expression Description 
x Undefined bit 
X Undefined multiple bits 
? Undefined, but depends on the device or pin status 
Device dependent The value depends on the device 
Pin value The value depends on the pin status 
 
Reset Value Conventions 
Expression Description 
0 Clears the register field 
1 Sets the register field 
x Dont care condition 
Warning: Some bits of control registers are driven by hardware or write operation only. As a result the indicated 
reset value and the read value after reset might be different. 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-1  
1 Product Overview 
1.1 Introduction 
Exynos 5250 is a system-on-a-chip (SoC) based on the 32-bit RISC processor for tablets and cell-phones. 
Designed with the 32 nm low power process, features of Exynos 5250 include: 
 Dual core CPU 
 Highest memory bandwidth 
 WQXGA display 
 1080p 60 frame video decoding and encoding hardware 
 3D graphics hardware 
 Image signal processor  
 High-speed interfaces such as eMMC4.5 and USB 3.0 
Exynos 5250 uses the Cortex-A15 dual core, which is 40 % DMIPS higher than Cortex-A9 core and its speed is 
1.7 GHz. It provides 12.8 GB/s memory bandwidth for heavy traffic operations such as 1080p video en/decoding, 
3D graphics display and high resolution image signal processing with WQXGA display. The application processor 
supports dynamic virtual address mapping, which helps software engineers to fully utilize the memory resources 
with ease. 
Exynos 5250 provides the best 3D graphics performance with wide range of APIs, such as OpenGL ES1.1, 2.0. 
You can use Exynos 5250s 3D cores as GPGPUs supported by OpenCL full profile. Superior 3D performance 
fully supports WQXGA display. Exynos 5250 supports not only low power eDP but also Panel-Self-Refresh (PSR) 
to make a low power system. The native dual display, in particular, supports WQXGA resolution of a main LCD 
display and 1080p 60 frame HDTV display throughout HDMI, simultaneously. Separate post processing pipeline 
enables Exynos 5250 to make a real display scenario. 
Exynos 5250 has integrated image signal processor (ISP). This ISP supports not only 8 mega pixel with 30 frames 
per second throughput but also has special functionalities such as 3-dimensional noise reduction (3DNR), video 
digital image stabilization (VDIS), and optical distortion compensation (ODC). The ISP helps to achieve zero-
shutter lag of camera shooting. 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-2  
Exynos 5250 lowers the Bill of Materials (BOM) by integrating these IPs:  
 DDR3/LPDDR3 interfaces 
 Image signal processor (ISP)  
 Eight channels of I2C for a variety of sensors  
 Variety of USB derivatives (USB Host or Device 3.0,USB Host or Device 2.0)  
 HSIC interfaces with PHY transceivers to connect with 802.11n, Ethernet, HSPA+, and 4G LTE modem 
 C2C for modem sharing DRAM 
The application processor also supports eMMC 4.5 interfaces and EF-NAND3.0 to increase the file system’s 
performance. 
Exynos 5250 is available as FCFBGA Single Chip Package (SCP), which has a 0.45 mm ball pitch. Package on 
Package (PoP) is also available with 0.4 mm ball pitch.  
 
  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-3  
1.2 Features 
The key features of Exynos 5250 include: 
 Cortex-A15 dual core subsystem with 64/128-bit SIMD NEON 
 32 KB (Instruction)/32 KB (Data) L1 Cache and 1 MB L2 Cache 
 Core frequency of 1.7 GHz at overdrive/2.0 GHz by binning 
 128-bit Multi-layered bus architecture 
 Internal ROM and RAM for secure booting, security, and general purposes 
 Memory Subsystem: 
 Two ports 32-bit 800 MHz LPDDR3/DDR3 Interfaces 
 Or two ports 32-bit 533 MHz LPDDR2 Interfaces 
 Eight-bit ITU 601 camera interface 
 Multi-format Video Hardware Codec: 1080p 60fps (capable of decoding and encoding MPEG-4/H.263/H.264 
and decoding only MPEG-2/VC1/VP8) 
 3D and 2D graphics hardware that supports OpenGL ES 1.1/2.0, OpenVG 1.1, and OpenCL 1.1 full profile 
 Image Signal Processor that supports BayerRGB up to 14-bit input with 16 MP 15 fps, 8 MP 30 fps through 
MIPI CSI2 & YUV 8-bit interfaces and special functionalities such as 3-dimensional noise reduction (3DNR), 
video digital image stabilization (VDIS), and optical distortion compensation (ODC) 
 JPEG Hardware Codec 
 LCD single display that supports max WQXGA (eDP)/WUXGA (MIPI DSI), 24 bpp RGB, YUV formats through 
low power eDP and MIPI DSI 
 Native dual display that supports WQXGA single LCD display and 1080p HDMI simultaneously 
 HDMI 1.4 interfaces with on-chip PHY 
 One port YUV 8-bit interfaces for camera input 
 Two ports (4-lanes) MIPI CSI2 interfaces 
 One port (4-lanes) low power eDP 
 One port (4-lanes) MIPI DSI  
 USB 3.0 device or Host 1-channel that supports SS (5 Gbps) with on-chip PHY 
 USB 2.0 Host or Device 1-channel that supports LS/FS/HS (1.5 Mbps/12 Mbps/480 Mbps) with on-chip PHY 
 USB HSIC 2-channel that supports 480 Mbps with on-chip PHY 
 SATA 1.0/2.0/3.0 interface 
 One channel eMMC 4.5  
 One channel SDIO 3.0  
 Two channel SD 2.0  
 Two channel EF-NAND 3.0 interface 
 Four channel high-speed UART (up to 3 Mbps data rate for Bluetooth 2.1 EDR and IrDA 1.0 SIR) 
 Three channel high-speed SPI  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-4  
 One channel AC-97, three channel PCM, and two channel 24-bit I2S audio interface that supports stereo 
channel audio and one channel 24-bit I2S audio interface that supports 5.1 channel audio 
 One channel S/PDIF interface support for digital audio 
 Four channel I2C interface support (up to 400 kbps) for PMIC, HDMI, and general-purpose multi-masters 
 Four channel HS-I2C (up to 3.1 Mbps) 
 Samsung Reconfiguration Processor supports low power audio play 
 Cortex-A5 low power co-processor 
 MIPI HSI version 1.0 that supports 200 Mbps full-duplex 
 C2C that supports through path between DRAM and MODEM 
 Security subsystem that supports hardware crypto accelerators 
 32-channel DMA controllers 
 Configurable GPIOs 
 Real-time clock, PLLs, timer with PWM, multi-core timer, and watchdog timer 
 
  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-5  
1.3 Block Diagram 
Figure 1-1 illustrates the block diagram of Exynos 5250. 
 
    Figure 1-1   Block Diagram of Exynos 5250 
 Memory/ Storage I/F
LPDDR3 and DDR3
32-bit 1600Mbps 2-port
Max. 12.8GBytes/sec
(LPDDR2 1066Mbps)
SRAM
1x eMMC 4.5(8-bit DDR)
1x SDIO 3.0(4-bit DDR)
2x SD 2.0(4-bit SDR)
2-ch EF-NAND
(8-bit DDR)
Graphics/ Video/ ISP
1080p 60fps codec:
VP8
3D HW: OpenGL ES,
OpenCL
2D HW
ISP & Post processors 
16MP ISP/ 8MP 30fps
3DNR, DIS, ODC, DRC
JPEG HW codec
Modem I/F
HSIC, MIPI HSI, C2C
System Peripheral
Virtual addressing
LP audio co-processor
Memory Interleaving
32x DMA
7-PLL, Timer, 4-PWM 
Display/ Camera
1-ch eDP output:
Single WQXGA
HDMI v1.4 output
2-ch 4-lane MIPI CSI2
or 1-ch 8-bit YUV input
14-bit Bayer input
8MP 30fps video
External Peripheral
4x UART
3x HS-SPI
8x I2C
3x 12S/PCM
1x AC97/S/PDIF
High Speed I/F
1 port USB 3.0 
(Device or Host)
1 port USB 2.0 
(Device or Host)
2x HSIC
1x SATA3
Multi-layer AXI/AHB Bus
Cortex-A15 Dual core
CPU 0
1.7GHz
32KB/32KB
NEON
CPU 1
1.7GHz
32KB/32KB
NEON
SCU
1MB L2 Cache
Secure
MEMTZPC
SYSMMUCrypto
Engine
MIPI DSI output:
Single SXGA or WXGA
or WUXGA  
						

							Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-6  
1.4 Product Details 
This section includes: 
 ARM Core 
 Memory Subsystem 
 Display Subsystem 
 Camera and General Scaling Subsystem 
 Graphics, Multimedia Acceleration Hardware and Image Signal Processor  
 Security Subsystem 
 High Speed Interfaces 
 External Peripheral