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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-77  
4.4.1.110 GPY5DAT 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0244, Reset Value = 0x00 
Name Bit Type Description Reset Value 
GPY5DAT[7:0] [7:0] RWX 
When you configure the port as input port, the 
corresponding bit is the pin state. When you configure 
the port as output port, the pin state is the same as the 
corresponding bit. W hen you configure the port as 
functional pin, the undefined value will be read. 
0x00 
 
4.4.1.111 GPY5PUD 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0248, Reset Value = 0x5555 
Name Bit Type Description Reset Value 
GPY5PUD[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x5555 
 
4.4.1.112 GPY5DRV 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x024C, Reset Value = 0x00_AAAA 
Name Bit Type Description Reset Value 
GPY5DRV[n] 
[2n + 1:2n] 
n = 0 to 7 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_AAAA 
[n + 16:16] 
n = 0 to 7 RW Reserved. Should be zero. 0x00_0000
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Exynos 5250_UM 4 Pad Control 
 4-78  
4.4.1.113 GPY5CONPDN 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0250, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPY5[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Output 0 
0x1 = Output 1 
0x2 = Input 
0x3 = Previous state 
0x00 
 
4.4.1.114 GPY5PUDPDN 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0254, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPY5[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x00
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-79  
4.4.1.115 GPY6CON 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0260, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GPY6CON[7] [31:28] RW 
0x0 = Input 
0x1 = Output 
0x2 = EBI_DATA[15] 
0x3 to 0xE = Reserved 
0xF = Reserved 
0x00 
GPY6CON[6] [27:24] RW 
0x0 = Input 
0x1 = Output 
0x2 = EBI_DATA[14] 
0x3 to 0xE = Reserved 
0xF = Reserved 
0x00 
GPY6CON[5] [23:20] RW 
0x0 = Input 
0x1 = Output 
0x2 = EBI_DATA[13] 
0x3 to 0xE = Reserved 
0xF = Reserved 
0x00 
GPY6CON[4] [19:16] RW 
0x0 = Input 
0x1 = Output 
0x2 = EBI_DATA[12] 
0x3 to 0xE = Reserved 
0xF = Reserved 
0x00 
GPY6CON[3] [15:12] RW 
0x0 = Input 
0x1 = Output 
0x2 = EBI_DATA[11] 
0x3 to 0xE = Reserved 
0xF = Reserved 
0x00 
GPY6CON[2] [11:8] RW 
0x0 = Input 
0x1 = Output 
0x2 = EBI_DATA[10] 
0x3 to 0xE = Reserved 
0xF = Reserved 
0x00 
GPY6CON[1] [7:4] RW 
0x0 = Input 
0x1 = Output 
0x2 = EBI_DATA[9] 
0x3 to 0xE = Reserved 
0xF = Reserved 
0x00 
GPY6CON[0] [3:0] RW 
0x0 = Input 
0x1 = Output 
0x2 = EBI_DATA[8] 
0x3 to 0xE = Reserved 
0xF = Reserved 
0x00
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Exynos 5250_UM 4 Pad Control 
 4-80  
4.4.1.116 GPY6DAT 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0264, Reset Value = 0x00 
Name Bit Type Description Reset Value 
GPY6DAT[7:0] [7:0] RWX 
When you configure the port as input port, the 
corresponding bit is the pin state. When you configure 
the port as output port, the pin state is the same as the 
corresponding bit. W hen you configure the port as 
functional pin, the undefined value will be read. 
0x00 
 
4.4.1.117 GPY6PUD 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0268, Reset Value = 0x5555 
Name Bit Type Description Reset Value 
GPY6PUD[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x5555 
 
4.4.1.118 GPY6DRV 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x026C, Reset Value = 0x00_AAAA 
Name Bit Type Description Reset Value 
GPY6DRV[n] 
[2n + 1:2n] 
n = 0 to 7 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_AAAA 
[n + 16:16] 
N = 0 to 7 RW Reserved. Should be zero. 0x00_0000
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Exynos 5250_UM 4 Pad Control 
 4-81  
4.4.1.119 GPY6CONPDN 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0270, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPY6[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Output 0 
0x1 = Output 1 
0x2 = Input 
0x3 = Previous state 
0x00 
 
4.4.1.120 GPY6PUDPDN 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0274, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPY6[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x00
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Exynos 5250_UM 4 Pad Control 
 4-82  
4.4.1.121 ETC0PUD 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0288, Reset Value = 0x04DD 
Name Bit Type Description Reset Value 
ETC0PUD[n] [2n + 1:2n] 
n = 0 to 5 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x04DD 
 
ETC0PUD[1:0] controls XjTRSTn. 
ETC0PUD[3:2] controls XjTMS. 
ETC0PUD[5:4] controls XjTCK. 
ETC0PUD[7:6] controls XjTDI. 
ETC0PUD[9:8] controls XjTDO. 
ETC0PUD[11:10] controls XjDBGSEL. 
 
4.4.1.122 ETC0DRV 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x028C, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
ETC0DRV[n] 
[2n + 1:2n] 
n = 0 to 5 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 5 RW Reserved. Should be zero. 0x00_0000 
 
ETC0DRV[1:0] controls XjTRSTn. 
ETC0DRV[3:2] controls XjTMS. 
ETC0DRV[5:4] controls XjTCK. 
ETC0DRV[7:6] controls XjTDI. 
ETC0DRV[9:8] controls XjTDO. 
ETC0DRV[11:10] controls XjDBGSEL.
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Exynos 5250_UM 4 Pad Control 
 4-83  
4.4.1.123 ETC6PUD 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x02A8, Reset Value = 0x30C0 
Name Bit Type Description Reset Value 
ETC6PUD[n] [2n + 1:2n] 
n = 0 to 6 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x30C0 
 
ETC6PUD[1:0] controls XnRESET. 
ETC6PUD[3:2] controls XCLKOUT. 
ETC6PUD[5:4] controls XnRSTOUT. 
ETC6PUD[7:6] controls XnWRESET. 
ETC6PUD[9:8] controls XRTCCLKO. 
ETC6PUD[11:10] controls XuhostPWREN. 
ETC6PUD[13:12] controls XuhostOVERCUR. 
 
4.4.1.124 ETC6DRV 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x02AC, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
ETC6DRV[n] 
[2n + 1:2n] 
n = 0 to 6 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 6 RW Reserved. Should be zero. 0x00_0000 
 
ETC6DRV[1:0] controls XnRESET. 
ETC6DRV[3:2] controls XCLKOUT. 
ETC6DRV[5:4] controls XnRSTOUT. 
ETC6DRV[7:6] controls XnWRESET. 
ETC6DRV[9:8] controls XRTCCLKO. 
ETC6DRV[11:10] controls XuhostPWREN. 
ETC6DRV[13:12] controls XuhostOVERCUR.
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Exynos 5250_UM 4 Pad Control 
 4-84  
4.4.1.125 ETC7PUD 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x02C8, Reset Value = 0x03C0 
Name Bit Type Description Reset Value 
ETC7PUD[n] [2n + 1:2n] 
n = 0 to 4 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x03C0 
 
ETC7PUD[1:0] controls XuotgDRVVBUS. 
ETC7PUD[3:2] controls Xusb3_VBUS_CTRL_U3. 
ETC7PUD[5:4] controls Xusb3_VBUS_CTRL_U2. 
ETC7PUD[7:6] controls Xusb3_PRTOVRCUR_U3. 
ETC7PUD[9:8] controls Xusb3_PRTOVRCUR_U2. 
 
4.4.1.126 ETC7DRV 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x02CC, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
ETC7DRV[n] 
[2n + 1:2n] 
n = 0 to 4 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 4 RW Reserved. Should be zero. 0x00_0000 
 
ETC7DRV[1:0] controls XuotgDRVVBUS. 
ETC7DRV[3:2] controls Xusb3_VBUS_CTRL_U3. 
ETC7DRV[5:4] controls Xusb3_VBUS_CTRL_U2. 
ETC7DRV[7:6] controls Xusb3_PRTOVRCUR_U3. 
ETC7DRV[9:8] controls Xusb3_PRTOVRCUR_U2.
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Exynos 5250_UM 4 Pad Control 
 4-85  
4.4.1.127 GPC4CON 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x02E0, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GPC4CON[6] [27:24] RW 
0x0 = Input  
0x1 = Output 
0x2 = SD_3_DATA[3], 
0x3 = SD_2_DATA[7], 
0x4 to 0xE = Reserved 
0xF = EXT_INT30[6] 
0x00 
GPC4CON[5] [23:20] RW 
0x0 = Input 
0x1 = Output 
0x2 = SD_3_DATA[2], 
0x3 = SD_2_DATA[6], 
0x4 to 0xE = Reserved 
0xF = EXT_INT30[5] 
0x00 
GPC4CON[4] [19:16] RW 
0x0 = Input 
0x1 = Output 
0x2 = SD_3_DATA[1], 
0x3 = SD_2_DATA[5], 
0x4 to 0xE = Reserved 
0xF = EXT_INT30[4] 
0x00 
GPC4CON[3] [15:12] RW 
0x0 = Input 
0x1 = Output 
0x2 = SD_3_DATA[0], 
0x3 = SD_2_DATA[4], 
0x4 to 0xE = Reserved 
0xF = EXT_INT30[3] 
0x00 
GPC4CON[2] [11:8] RW 
0x0 = Input 
0x1 = Output 
0x2 = SD_3_CDn 
0x3= Reserved 
0x4 = SD_3_nRESET_OUT 
0x5 = SD_3_CARD_INT_n 
0x6 to 0xE = Reserved 
0xF = EXT_INT30[2] 
0x00 
GPC4CON[1] [7:4] RW 
0x0 = Input 
0x1 = Output 
0x2 = SD_3_CMD 
0x3 to 0xE = Reserved 
0xF = EXT_INT30[1] 
0x00 
GPC4CON[0] [3:0] RW 
0x0 = Input 
0x1 = Output 
0x2 = SD_3_CLK 
0x3 to 0xE = Reserved 
0xF = EXT_INT30[0] 
0x00
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Exynos 5250_UM 4 Pad Control 
 4-86  
4.4.1.128 GPC4DAT 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x02E4, Reset Value = 0x00 
Name Bit Type Description Reset Value 
GPC4DAT[6:0] [6:0] RWX 
When the port is configured as input port, the 
corresponding bit is the pin state. When the port is 
configured as output port, the pin state is the same as 
the corresponding bit. W hen the port is configured as 
functional pin, the undefined value will be read. 
0x00 
 
4.4.1.129 GPC4PUD 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x02E8, Reset Value = 0x1555 
Name Bit Type Description Reset Value 
GPC4PUD[n] [2n + 1:2n] 
n = 0 to 6 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x1555 
 
4.4.1.130 GPC4DRV 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x02EC, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
GPC4DRV[n] 
[2n + 1:2n] 
n = 0 to 6 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 6 RW Reserved. Should be zero. 0x00_0000
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