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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-117  
4.4.1.157 EXT_INT6_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0828, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN6[3] [31] RW 
Enables Filter for EXT_INT6[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[3] [30:24] RW Filtering width of EXT_INT6[3] 0x00 
FLTEN6[2] [23] RW 
Enables Filter for EXT_INT6[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[2] [22:16] RW Filtering width of EXT_INT6[2] 0x00 
FLTEN6[1] [15] RW 
Enables Filter for EXT_INT6[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[1] [14:8] RW Filtering width of EXT_INT6[1] 0x00 
FLTEN6[0] [7] RW 
Enables Filter for EXT_INT6[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[0] [6:0] RW Filtering width of EXT_INT6[0] 0x00 
 
4.4.1.158 EXT_INT6_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x082C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-118  
4.4.1.159 EXT_INT7_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0830, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN7[3] [31] RW 
Enables Filter for EXT_INT7[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH7[3] [30:24] RW Filtering width of EXT_INT7[3] 0x00 
FLTEN7[2] [23] RW 
Enables Filter for EXT_INT7[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH7[2] [22:16] RW Filtering width of EXT_INT7[2] 0x00 
FLTEN7[1] [15] RW 
Enables Filter for EXT_INT7[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH7[1] [14:8] RW Filtering width of EXT_INT7[1] 0x00 
FLTEN7[0] [7] RW 
Enables Filter for EXT_INT7[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH7[0] [6:0] RW Filtering width of EXT_INT7[0] 0x00 
 
4.4.1.160 EXT_INT7_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0834, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-119  
4.4.1.161 EXT_INT8_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0838, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN8[3] [31] RW 
Enables Filter for EXT_INT8[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[3] [30:24] RW Filtering width of EXT_INT8[3] 0x00 
FLTEN8[2] [23] RW 
Enables Filter for EXT_INT8[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[2] [22:16] RW Filtering width of EXT_INT8[2] 0x00 
FLTEN8[1] [15] RW 
Enables Filter for EXT_INT8[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[1] [14:8] RW Filtering width of EXT_INT8[1] 0x00 
FLTEN8[0] [7] RW 
Enables Filter for EXT_INT8[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[0] [6:0] RW Filtering width of EXT_INT8[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-120  
4.4.1.162 EXT_INT8_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x083C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN8[3] [31] RW 
Enables Filter for EXT_INT8[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[3] [30:24] RW Filtering width of EXT_INT8[3] 0x00 
FLTEN8[2] [23] RW 
Enables Filter for EXT_INT8[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[2] [22:16] RW Filtering width of EXT_INT8[2] 0x00 
FLTEN8[1] [15] RW 
Enables Filter for EXT_INT8[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[1] [14:8] RW Filtering width of EXT_INT8[1] 0x00 
FLTEN8[0] [7] RW 
Enables Filter for EXT_INT8[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH8[0] [6:0] RW Filtering width of EXT_INT8[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-121  
4.4.1.163 EXT_INT9_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0840, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN9[3] [31] RW 
Enables Filter for EXT_INT9[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[3] [30:24] RW Filtering width of EXT_INT9[3] 0x00 
FLTEN9[2] [23] RW 
Enables Filter for EXT_INT9[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[2] [22:16] RW Filtering width of EXT_INT9[2] 0x00 
FLTEN9[1] [15] RW 
Enables Filter for EXT_INT9[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[1] [14:8] RW Filtering width of EXT_INT9[1] 0x00 
FLTEN9[0] [7] RW 
Enables Filter for EXT_INT9[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH9[0] [6:0] RW Filtering width of EXT_INT9[0] 0x00 
 
4.4.1.164 EXT_INT9_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0844, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
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Exynos 5250_UM 4 Pad Control 
 4-122  
4.4.1.165 EXT_INT10_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0848, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN10[3] [31] RW 
Enables Filter for EXT_INT10[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH10[3] [30:24] RW Filtering width of EXT_INT10[3] 0x00 
FLTEN10[2] [23] RW 
Enables Filter for EXT_INT10[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH10[2] [22:16] RW Filtering width of EXT_INT10[2] 0x00 
FLTEN10[1] [15] RW 
Enables Filter for EXT_INT10[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH10[1] [14:8] RW Filtering width of EXT_INT10[1] 0x00 
FLTEN10[0] [7] RW 
Enables Filter for EXT_INT10[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH10[0] [6:0] RW Filtering width of EXT_INT10[0] 0x00 
 
4.4.1.166 EXT_INT10_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x084C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0x00=
FLTEN10[6]=[23]=RW=
Enables Filter=for EXT_INT10[6]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH10[6]=[22:16]=RW=Filtering width of EXT_INT10[6]=0x00=
FLTEN10[5]=[15]=RW=
Enables Filter=for EXT_INT10[5]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH10[5]=[14:8]=RW=Filtering width of EXT_INT10[5]=0x00=
FLTEN10[4]=[7]=RW=
Enables Filter=for EXT_INT10[4]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH10[4]=[6:0]=RW=Filtering width of EXT_INT10[4]=0x00=
=
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Exynos 5250_UM 4 Pad Control 
 4-123  
4.4.1.167 EXT_INT11_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0850, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN11[3] [31] RW 
Enables Filter for EXT_INT11[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH11[3] [30:24] RW Filtering width of EXT_INT11[3] 0x00 
FLTEN11[2] [23] RW 
Enables Filter for EXT_INT11[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH11[2] [22:16] RW Filtering width of EXT_INT11[2] 0x00 
FLTEN11[1] [15] RW 
Enables Filter for EXT_INT11[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH11[1] [14:8] RW Filtering width of EXT_INT11[1] 0x00 
FLTEN11[0] [7] RW 
Enables Filter for EXT_INT11[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH11[0] [6:0] RW Filtering width of EXT_INT11[0] 0x00 
 
4.4.1.168 EXT_INT11_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0854, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0x00=
FLTEN11[6]=[23]=RW=
Enables Filter=for EXT_INT11[6]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH11[6]=[22:16]=RW=Filtering width of EXT_INT11[6]=0x00=
FLTEN11[5]=[15]=RW=
Enables Filter=for EXT_INT11[5]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH11[5]=[14:8]=RW=Filtering width of EXT_INT11[5]=0x00=
FLTEN11[4]=[7]=RW=
Enables Filter=for EXT_INT11[4]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH11[4]=[6:0]=RW=Filtering width of EXT_INT11[4]=0x00=
=
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Exynos 5250_UM 4 Pad Control 
 4-124  
4.4.1.169 EXT_INT12_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0858, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN12[3] [31] RW 
Enables Filter for EXT_INT12[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH12[3] [30:24] RW Filtering width of EXT_INT12[3] 0x00 
FLTEN12[2] [23] RW 
Enables Filter for EXT_INT12[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH12[2] [22:16] RW Filtering width of EXT_INT12[2] 0x00 
FLTEN12[1] [15] RW 
Enables Filter for EXT_INT12[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH12[1] [14:8] RW Filtering width of EXT_INT12[1] 0x00 
FLTEN12[0] [7] RW 
Enables Filter for EXT_INT12[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH12[0] [6:0] RW Filtering width of EXT_INT12[0] 0x00 
 
 
4.4.1.170 EXT_INT12_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x085C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-125  
4.4.1.171 EXT_INT13_FLTCON0 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0860, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN13[3] [31] RW 
Enables Filter for EXT_INT13[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH13[3] [30:24] RW Filtering width of EXT_INT13[3] 0x00 
FLTEN13[2] [23] RW 
Enables Filter for EXT_INT13[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH13[2] [22:16] RW Filtering width of EXT_INT13[2] 0x00 
FLTEN13[1] [15] RW 
Enables Filter for EXT_INT13[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH13[1] [14:8] RW Filtering width of EXT_INT13[1] 0x00 
FLTEN13[0] [7] RW 
Enables Filter for EXT_INT13[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH13[0] [6:0] RW Filtering width of EXT_INT13[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-126  
4.4.1.172 EXT_INT13_FLTCON1 
 Base Address: 0x1140_0000 
 Address = Base Address + 0x0864, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN13[7] [31] RW 
Enables Filter for EXT_INT13[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH13[7] [30:24] RW Filtering width of EXT_INT13[7] 0x00 
FLTEN13[6] [23] RW 
Enables Filter for EXT_INT13[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH13[6] [22:16] RW Filtering width of EXT_INT13[6] 0x00 
FLTEN13[5] [15] RW 
Enables Filter for EXT_INT13[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH13[5] [14:8] RW Filtering width of EXT_INT13[5] 0x00 
FLTEN13[4] [7] RW 
Enables Filter for EXT_INT13[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH13[4] [6:0] RW Filtering width of EXT_INT13[4] 0x00
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