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Samsung Exynos 5 User Manual

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Exynos 5250_UM 7 Interrupt Combiner 
 7-43  
7.5.1.32 IMSR7 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x007C, Reset Value = Undefined  
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=–=
EINTx15]=[25]=o=Masked interrupt=pending status==
If the corresponding interrupt enable bit is=0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx14]=[24]=o=–=
RSVD=x23:18]=–=Reserved=–=
EINTx13]=x17]=o=Masked interrupt=pending status==
If the=corresponding interrupt enable bit is 0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx12]=x16]=o=–=
RSVD=x15:10]=–=Reserved=–=
EINTx11]=x9]=o=Masked interrupt=pending status==
If the corresponding=interrupt enable bit is 0,=
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx10]=[8]=o=–=
RSVD=x7:2]=–=Reserved=–=
EINTx9]=x1]=o=Masked interrupt=pending status==
If the corresponding interrupt enable=bit is 0, 
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
EINTx8]=[0]=o=–=
=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-44  
7.5.1.33 CIPSR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0100, Reset Value = Undefined 
Name Bit Type Description Reset Value 
INTG31 [31] R 
Combined interrupt pending status  
0 = The combined interrupt is not pending. 
1 = The combined interrupt is pending. This 
indicates that the corresponding interrupt request 
to the GIC is asserted. 
–=
INTG30=x30]=o=–=
INTG29=x29]=o=–=
INTG28=x28]=o=–=
INTG27=x27]=o=–=
INTG26=x26]=o=–=
INTG25=x25]=o=–=
INTG24=x24]=o=–=
INTG23=x23]=o=–=
INTG22=x22]=o=–=
INTG21=x21]=o=–=
INTd20=x20]=o=–=
INTG19=x19]=o=–=
INTG18=x18]=o=–=
INTG17=[17]=o=–=
INTG1S=x16]=o=–=
INTG15=[15]=o=–=
INTG14=[14]=o=–=
INTG13=[13]=o=–=
INTG12=[12]=o=–=
INTG11=[11]=o=–=
INTG10=[10]=o=–=
INTG9=[9]=o=–=
INTG8=[8]=o=–=
INTG7=[7]=o=–=
INTGS=[6]=o=–=
INTG5=[5]=o=–=
INTG4=[4]=o=–=
INTG3=[3]=o=–=
INTG2=[2]=o=–=
INTG1=[1]=o=–=
INTG0=[0]=o=–=
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Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-1  
8 DMA (Direct Memory Access) Controller 
8.1 Overview 
Exynos 5250 has three DMA controller: 
 Two DMA controller transfers from Memory to Memory. (MDMA0, MDMA1) 
 One DMA controller transfers Peripheral-to-Memory and vice-versa. (PDMA) 
The MDMA Controller consists of one DMA330 and a few logics. The PDMA Controller consists of two DMA330 
(PDMA0 and PDMA1) and dma_mapper. 
Figure 8-1 illustrates the two type of DMA controller. 
 
    Figure 8-1   Two type of DMA Controller 
 PDMA0 (DMA330r1p1)PDMA1 (DMA330r1p1)
dma_mapper
REQ from IPs
IRQ to Interrupt ControllerIRQ to Interrupt Controller
PDMA
MDMA0 (DMA330r1p1)
IRQ to Interrupt Controller
MDMA1 (DMA330r1p1)
IRQ to Interrupt Controller
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Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-2  
8.2 Features 
Features of DMA Controller are: 
Features MDMA PDMA 
Supports data size Up to double word (64-bit) Up to word (32-bit) 
Supports burst size Up to 16 burst Up to 8 burst 
Supports channel 8 channels at the same time 16 channels at the same time 
 
Refer these features for DMA and for writing DMA assembly code. 
NOTE: DMA Controller sends only one interrupt to Interrupt Controller for each DMA although each DMA module has 32 
interrupt sources.  
 
Table 8-1 describes DMA request mapping table. 
Table 8-1   DMA Request Mapping Table 
Module No.  Module No.  Module No.  
PDMA0 
31 MIPI_HSI_6 
PDMA1 
31 MIPI_HSI_7 
MDMA 
31 – 
30 MIPI_HSI_4 30 MIPI_HSI_5 30 – 
29 MIPI_HSI_2 29 MIPI_HSI_3 29 – 
28 MIPI_HSI_0 28 MIPI_HSI_1 28 – 
27 AC_PCMout 27 Reserved 27 – 
26 AC_PCMin 26 Reserved 26 – 
25 AC_MICin 25 Reserved 25 – 
24 Reserved 24 Reserved 24 – 
23 Reserved 23 Reserved 23 – 
22 Reserved 22 Reserved 22 – 
21 Reserved 21 Reserved 21 – 
20 Reserved 20 Reserved 20 – 
19 Reserved 19 Reserved 19 – 
18 Reserved 18 UART3_TX 18 – 
17 Reserved 17 UART3_RX 17 – 
16 UART2_TX 16 UART1_TX 16 – 
15 UART2_RX 15 UART1_RX 15 – 
14 UART0_TX 14 UART0_TX 14 – 
13 UART0_RX 13 UART0_RX 13 – 
12 I2S2_TX 12 I2S1_TX 12 – 
11 I2S2_RX 11 I2S1_RX 11 –
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Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-3  
Module No.  Module No.  Module No.  
10 I2S0_TX 10 I2S0_TX 10 – 
9 I2S0_RX 9 I2S0_RX 9 – 
8 I2S0S_TX 8 I2S0S_TX 8 – 
7 SPI2_TX 7 SPDIF 7 – 
6 SPI2_RX 6 PW M 6 – 
5 SPI0_TX 5 SPI1_TX 5 – 
4 SPI0_RX 4 SPI1_RX 4 – 
3 PCM2_TX 3 PCM1_TX 3 – 
2 PCM2_RX 2 PCM1_RX 2 – 
1 PCM0_TX 1 PCM0_TX 1 – 
0 PCM0_RX 0 PCM0_RX 0 – 
 
Ensure to verify the CLKGATE status when PDMA0 or PDMA1 are enabled.
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Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-4  
8.3 Functional Description 
8.3.1 Instruction 
Please refer to the PL330 TRM, AMBA DMA Controller DMA-330 technical reference manual revision r1p1 from 
ARM®.  
 
8.3.1.1 Security Scheme 
MDMA controller and PDMA controller run in the non-secure mode only. 
 
8.3.1.2 Summary 
 Configuring DMAC: 
You can configure DMAC with up to eight DMA channels. Each channel is capable of supporting a single 
concurrent thread of DMA operation. Additionally, there is a single DMA manager thread to initialize the DMA 
channel thread. 
 
 Channel thread: 
Each channel thread can operate DMA. Ensure to write the assembly code accordingly. When you require a 
number of independent DMA channels, you must write a number of assembly codes for each channel. 
Assemble these channels, link them into one file, and load this file into memory.
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Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-5  
8.4 Register Description 
Most Special Function Registers (SFRs) are read-only. The main role of SFR is to verify the DMA330 status. 
There are many SFRs for DMA330. In this section describes Exynos 5250-specific SFRs only. Please refer to the 
PL330 TRM, AMBA DMA Controller DMA-330 technical reference manual revision r1p1 from ARM®  for more 
information. 
 
8.4.1 Register Map Summary 
 Base Address: 0x1080_0000 (MDMA0) 
 Base Address: 0x11C1_0000 (MDMA1) 
Register Offset Description Reset Value 
MDMA0/MDMA1 
DSR 0x0000 Specifies the DMA status register.  0x0000_0200 
DPC 0x0004 Specifies the DMA program counter register. 0x0 
RSVD 0x0008 
to 0x001C Reserved Undefined 
INTEN 0x0020 Specifies the interrupt enable register.  0x0 
ES 0x0024 Specifies the event status register.  0x0 
INTSTATUS 0x0028 Specifies the interrupt status register. 0x0 
INTCLR 0x002C Specifies the interrupt clear register.  0x0 
FSM 0x0030 Specifies the fault status DMA manager register. 0x0 
FSC 0x0034 Specifies the fault status DMA channel register.  0x0 
FTM 0x0038 Specifies the fault type DMA manager register.  0x0 
RSVD 0x003C Reserved Undefined 
FTC0 0x0040 Specifies the fault type for DMA channel 0. 0x0 
FTC1 0x0044 Specifies the fault type for DMA channel 1. 0x0 
FTC2 0x0048 Specifies the fault type for DMA channel 2. 0x0 
FTC3 0x004C Specifies the fault type for DMA channel 3. 0x0 
FTC4 0x0050 Specifies the fault type for DMA channel 4. 0x0 
FTC5 0x0054 Specifies the fault type for DMA channel 5. 0x0 
FTC6 0x0058 Specifies the fault type for DMA channel 6. 0x0 
FTC7 0x005C Specifies the fault type for DMA channel 7. 0x0 
RSVD 0x0060 
to 0x00FC Reserved Undefined 
CS0 0x0100 Specifies the channel status for DMA channel 0. 0x0 
CS1 0x0108 Specifies the channel status for DMA channel 1. 0x0 
CS2 0x0110 Specifies the channel status for DMA channel 2. 0x0 
CS3 0x0118 Specifies the channel status for DMA channel 3. 0x0 
CS4 0x0120 Specifies the channel status for DMA channel 4. 0x0
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Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-6  
Register Offset Description Reset Value 
CS5 0x0128 Specifies the channel status for DMA channel 5. 0x0 
CS6 0x0130 Specifies the channel status for DMA channel 6. 0x0 
CS7 0x0138 Specifies the channel status for DMA channel 7. 0x0 
CPC0 0x0104 Specifies the channel PC for DMA channel 0. 0x0 
CPC1 0x010C Specifies the channel PC for DMA channel 1. 0x0 
CPC2 0x0114 Specifies the channel PC for DMA channel 2. 0x0 
CPC3 0x011C Specifies the channel PC for DMA channel 3. 0x0 
CPC4 0x0124 Specifies the channel PC for DMA channel 4. 0x0 
CPC5 0x012C Specifies the channel PC for DMA channel 5. 0x0 
CPC6 0x0134 Specifies the channel PC for DMA channel 6. 0x0 
CPC7 0x013C Specifies the channel PC for DMA channel 7. 0x0 
RSVD 0x0140 
to 0x03FC Reserved Undefined 
SA_0 0x0400 Specifies the source address for DMA channel 0. 0x0 
SA_1 0x0420 Specifies the source address for DMA channel 1. 0x0 
SA_2 0x0440 Specifies the source address for DMA channel 2. 0x0 
SA_3 0x0460 Specifies the source address for DMA channel 3. 0x0 
SA_4 0x0480 Specifies the source address for DMA channel 4. 0x0 
SA_5 0x04A0 Specifies the source address for DMA channel 5. 0x0 
SA_6 0x04C0 Specifies the source address for DMA channel 6. 0x0 
SA_7 0x04E0 Specifies the source address for DMA channel 7. 0x0 
DA_0 0x0404 Specifies the destination address for DMA channel 0. 0x0 
DA_1 0x0424 Specifies the destination address for DMA channel 1. 0x0 
DA_2 0x0444 Specifies the destination address for DMA channel 2. 0x0 
DA_3 0x0464 Specifies the destination address for DMA channel 3. 0x0 
DA_4 0x0484 Specifies the destination address for DMA channel 4. 0x0 
DA_5 0x04A4 Specifies the destination address for DMA channel 5. 0x0 
DA_6 0x04C4 Specifies the destination address for DMA channel 6. 0x0 
DA_7 0x04E4 Specifies the destination address for DMA channel 7. 0x0 
CC_0 0x0408 Specifies the channel control for DMA channel 0. 0x0 
CC_1 0x0428 Specifies the channel control for DMA channel 1. 0x0 
CC_2 0x0448 Specifies the channel control for DMA channel 2. 0x0 
CC_3 0x0468 Specifies the channel control for DMA channel 3. 0x0 
CC_4 0x0488 Specifies the channel control for DMA channel 4. 0x0 
CC_5 0x04A8 Specifies the channel control for DMA channel 5. 0x0 
CC_6 0x04C8 Specifies the channel control for DMA channel 6. 0x0 
CC_7 0x04E8 Specifies the channel control for DMA channel 7. 0x0
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Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-7  
Register Offset Description Reset Value 
LC0_0 0x040C Specifies the loop counter 0 for DMA channel 0. 0x0 
LC0_1 0x042C Specifies the loop counter 0 for DMA channel 1. 0x0 
LC0_2 0x044C Specifies the loop counter 0 for DMA channel 2. 0x0 
LC0_3 0x046C Specifies the loop counter 0 for DMA channel 3. 0x0 
LC0_4 0x048C Specifies the loop counter 0 for DMA channel 4. 0x0 
LC0_5 0x04AC Specifies the loop counter 0 for DMA channel 5. 0x0 
LC0_6 0x04CC Specifies the loop counter 0 for DMA channel 6. 0x0 
LC0_7 0x04EC Specifies the loop counter 0 for DMA channel 7. 0x0 
LC1_0 0x0410 Specifies the loop counter 1 for DMA channel 0. 0x0 
LC1_1 0x0430 Specifies the loop counter 1 for DMA channel 1. 0x0 
LC1_2 0x0450 Specifies the loop counter 1 for DMA channel 2. 0x0 
LC1_3 0x0470 Specifies the loop counter 1 for DMA channel 3. 0x0 
LC1_4 0x0490 Specifies the loop counter 1 for DMA channel 4. 0x0 
LC1_5 0x04B0 Specifies the loop counter 1 for DMA channel 5. 0x0 
LC1_6 0x04D0 Specifies the loop counter 1 for DMA channel 6. 0x0 
LC1_7 0x04F0 Specifies the loop counter 1 for DMA channel 7. 0x0 
RSVD 0x0414 
to 0x041C Reserved Undefined 
RSVD 0x0434 
to 0x043C Reserved Undefined 
RSVD 0x0454 
to 0x045C Reserved Undefined 
RSVD 0x0474 
to 0x047C Reserved Undefined 
RSVD 0x0494 
to 0x049C Reserved Undefined 
RSVD 0x04B4 
to 0x04BC Reserved Undefined 
RSVD 0x04D4 
to 0x04DC Reserved Undefined 
RSVD 0x04F4 
to 0x0CFC Reserved Undefined 
DBGSTATUS 0x0D00 Specifies the debug status register. 0x0 
DBGCMD 0x0D04 Specifies the debug command register Undefined 
DBGINST0 0x0D08 Specifies the debug Instruction-0 register. Undefined 
DBGINST1 0x0D0C Specifies the debug Instruction-1 register.  Undefined 
CR0 0x0E00 Specifies the configuration register 0.  0x003E_0075 
CR1 0x0E04 Specifies the configuration register 1. 0x0000_0075 
CR2 0x0E08 Specifies the configuration register 2. 0x0
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Exynos 5250_UM 8 DMA (Direct Memory Access) Controller 
 8-8  
Register Offset Description Reset Value 
CR3 0x0E0C Specifies the configuration register 3. 0xFFFF_FFFF 
CR4 0x0E10 Specifies the configuration register 4.  0x0000_0001 
CRDn 0x0E14 Specifies the configuration register Dn. 0x03F7_3733 
RSVD 0x0E18 
to 0x0E7C Reserved Undefined 
WD 0x0E80 Watchdog register. 0x0 
periph_id_n 0x0FE0 
to 0x0FEC Specifies the peripheral Identification registers 0-3. Configuration-
dependent 
pcell_id_n 0x0FF0 
to 0x0FFC Specifies the prime cell Identification registers 0-3. Configuration-
dependent 
NOTE: The SFR description shows only the restricted and fixed part of some SFR. PL330 TRM shows detailed information of 
other parts and other SFRs.
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