Samsung Exynos 5 User Manual
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Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-48
5.9.1.1 APLL_LOCK
Base Address: 0x1001_0000
Address = Base Address + 0x0000, Reset Value = 0x0000_0FFF
Name Bit Type Description Reset Value
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required=period(in=cycles)=to generate a stable=
clock output=
The maximum lock time can be up to 250= PDIV
cycles of PLLs FIN (XXTI).
0xF_FFFF](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-413.png "Page 414
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-48
5.9.1.1 APLL_LOCK
Base Address: 0x1001_0000
Address = Base Address + 0x0000, Reset Value = 0x0000_0FFF
Name Bit Type Description Reset Value
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required=period(in=cycles)=to generate a stable=
clock output=
The maximum lock time can be up to 250= PDIV
cycles of PLLs FIN (XXTI).
0xF_FFFF")
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Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-49
5.9.1.2 APLL_CON0
Base Address: 0x1001_0000
Address = Base Address + 0x0100, Reset Value = 0x00C8_0601
Name Bit Type Description Reset Value
ENABLE [31] RW
PLL Enable control
0 = Disables PLL
1 = Enables PLL
0x0
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL Locking indication=
0 = Unlocks PLi=
1 = Locks PLi=
0x0=
RSVD=x28]=–=Reserved=0x0=
FSEL=[27]=RW=
Monitoring=Frequency Select pin=
0 = FVCO_OUT== FREF=
1 = FVCO_OUT = FVCl=...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-414.png "Page 415
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-49
5.9.1.2 APLL_CON0
Base Address: 0x1001_0000
Address = Base Address + 0x0100, Reset Value = 0x00C8_0601
Name Bit Type Description Reset Value
ENABLE [31] RW
PLL Enable control
0 = Disables PLL
1 = Enables PLL
0x0
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL Locking indication=
0 = Unlocks PLi=
1 = Locks PLi=
0x0=
RSVD=x28]=–=Reserved=0x0=
FSEL=[27]=RW=
Monitoring=Frequency Select pin=
0 = FVCO_OUT== FREF=
1 = FVCO_OUT = FVCl=...")
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Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-50
Do not set the value of PDIV[5:0] or MDIV[9:0] to all zeros.
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on
recommended PMS values.
SDIV[2:0] controls division ratio of Scaler as described in Table 5-15.
Table 5-15 lists the Division Ratio of Scaler.
Table 5-15 Division Ratio of Scaler
S[2:0] Division Ratio
000 2^0 = 1
001 2^1 = 2
010 2^2 = 4
011 2^3 = 8
100 2^4 = 16
101...](http://img.usermanuals.tech/thumb/66/99535/w64_exynos-5-user-manual-1509363421_d-415.png "Page 416
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-50
Do not set the value of PDIV[5:0] or MDIV[9:0] to all zeros.
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on
recommended PMS values.
SDIV[2:0] controls division ratio of Scaler as described in Table 5-15.
Table 5-15 lists the Division Ratio of Scaler.
Table 5-15 Division Ratio of Scaler
S[2:0] Division Ratio
000 2^0 = 1
001 2^1 = 2
010 2^2 = 4
011 2^3 = 8
100 2^4 = 16
101...")
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-45 Base Address: 0x1003_0000 Register Offset Description Reset Value RSVD 0x0000 to 0x000C Reserved Undefined BPLL_LOCK 0x0010 Control PLL Locking period of BPLL 0x0000_0FFF RSVD 0x0014 to 0x010C Reserved Undefined BPLL_CON0 0x0110 Control PLL output frequency for BPLL 0x00C8_0601 BPLL_CON1 0x0114 Control PLL AFC 0x0020_3800 RSVD 0x0118 to 0x01FC Reserved Undefined CLK_SRC_CDREX 0x0200 Select Clock Source for CMU_CDREX 0x0000_0000 RSVD 0x0204 to 0x03FC Reserved Undefined CLK_MUX_STAT _CDREX 0x0400 Clock MUX Status for CMU_CDREX 0x0000_1111 RSVD 0x0404 to 0x04FC Reserved Undefined CLK_DIV_CDREX 0x0500 Set Clock Divider ratio for CMU_CDREX 0x0000_0000 RSVD 0x0504 to 0x05FC Reserved Undefined CLK_DIV_STAT _CDREX 0x0600 Clock Divider Status for CMU_CDREX 0x0000_0000 RSVD 0x0604 to 0x08FC Reserved Undefined CLK_GATE_IP_CDREX 0x0900 Control IP Clock Gating for DMC_BLK (CDREX) 0xFFFF_FFFF RSVD 0x0904 to 0x090C Reserved Undefined RSVD 0x0904 to 0x0910 Reserved Undefined DMC_FREQ_CTRL 0x0914 DMC Frequency Control register 0x0000_0000 RSVD 0x0918 to 0x0918 Reserved Undefined DREX2_PAUSE 0x091C Pause function for DREX2 0x7FFC_7FFF RSVD 0x0920 to 0x09FC Reserved Undefined CLKOUT_CMU _CDREX 0x0A00 CLKOUT control register 0x0001_0000 CLKOUT_CMU _CDREX_DIV_STAT 0x0A04 Clock Divider Status for CLKOUT 0x0000_0000 RSVD 0x0A08 to 0x0A0C Reserved Undefined
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-46 Register Offset Description Reset Value LPDDR3PHY_CTRL 0x0A10 Reset for LPDDR3HPHY. This reset is used for DDR3 memory 0x0000_0001 RSVD 0x0A14 to 0x0A1C Reserved Undefined LPDDR3PHY_CON3 0x0A20 DREX ADDR pin Change 0x0000_0000 PLL_DIV2_SEL 0x0A24 Selection for PLL_FOUT 0x0000_0000 RSVD 0x0A28 to 0xFFFC Reserved Undefined
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-47 SFRs consist of nine parts. The SFRs with address 0x1001_0000 to 0x1001_3FFF control clock-related logics for CPU block. They control APLL, Clock Source Selection, and Clock Divider Ratio for CPU-related logics. The SFRs with address 0x1001_4000 to 0x1001_7FFF control clock-related logics for DMC block (part 1). They control MPLL, Clock Source Selection, Clock Divider Ratio, and Clock Gating for DMC peripheral sub- block. The SFRs with address 0x1001_8000 to 0x1001_BFFF control clock-related logics for DMC block (part 2). They control Clock Source Selection, Clock Divider Ratio, and Clock Gating for ACP sub-block. The SFRs with address 0x1001_C000 to 0x1001_FFFF control clock-related logics for ISP block. They control Clock Source Selection, Clock Divider Ratio, and Clock Gating. The SFRs with address 0x1002_0000 to 0x1002_3FFF control clock-related logics for MFC, G3D, DISP1, GSCL, FSYS, PERIC, and PERIS blocks. They control CPLL, EPLL, GPLL and VPLL, Clock Source Selection, Clock Divider Ratio, and Clock Gating. The SFRs with address 0x1002_4000 to 0x1002_7FFF control clock-related logics for LEX block. They control Clock Source Selection, Clock Divider Ratio, and Clock Gating. The SFRs with address 0x1002_8000 to 0x1002_BFFF control clock-related logics for R0X block. They control Clock Source Selection, Clock Divider Ratio, and Clock Gating. The SFRs with address 0x1002_C000 to 0x1002_FFFF control clock-related logics for R1X block. They control Clock Source Selection, Clock Divider Ratio, and Clock Gating. The SFRs with address 0x1003_0000 to 0x1003_3FFF control clock-related logics for DMC block (part 3). They control BPLL, Clock Source Selection, Clock Divider Ratio, and Clock Gating for DREXII in CDREX sub- block.
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-48 5.9.1.1 APLL_LOCK Base Address: 0x1001_0000 Address = Base Address + 0x0000, Reset Value = 0x0000_0FFF Name Bit Type Description Reset Value RSVD [31:20] –=Reserved=0x0= PLL_LOCKTIME=[19:0]=RW= Required=period(in=cycles)=to generate a stable= clock output= The maximum lock time can be up to 250= PDIV cycles of PLLs FIN (XXTI). 0xF_FFFF
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-49 5.9.1.2 APLL_CON0 Base Address: 0x1001_0000 Address = Base Address + 0x0100, Reset Value = 0x00C8_0601 Name Bit Type Description Reset Value ENABLE [31] RW PLL Enable control 0 = Disables PLL 1 = Enables PLL 0x0 RSVD [30] –=Reserved=0x0= LOCKED=[29]=o= PLL Locking indication= 0 = Unlocks PLi= 1 = Locks PLi= 0x0= RSVD=x28]=–=Reserved=0x0= FSEL=[27]=RW= Monitoring=Frequency Select pin= 0 = FVCO_OUT== FREF= 1 = FVCO_OUT = FVCl= 0x0= RSVD=[26]=–=Reserved=0x0= MDIV=[25:16]=RW=PLL M Divide value=0xC8= RSVD=[15:14]=–=Reserved=0x0= PDIV=[13:8]=RW=PLL P Divide value=0xS= RSVD=[7:3]=–=Reserved=0x0= SDIV=[2:0]=RW=PLL S Divide value=0x1= = The reset value of=APLL_CON0=generates 400=MHz output clock=for the input clock frequency of=24=MHz.= Equation to calculate the=output frequency=is:= FOUT = MDIV FIN/(PDIV 2SDIV) MDIV, PDIV, SDIV for APLL should conform to these conditions: PDIV: 1 PDIV 63 MDIV: 64 MDIV 1023 SDIV: 0 SDIV 5 Fref (= FIN/PDIV): 2 MHz Fref 12 MHz FVCO (= MDIV FIN/PDIV): 700 MHz FVCO 1700 MHz FOUT: 21.9 MHz FOUT 1700 MHz
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-50 Do not set the value of PDIV[5:0] or MDIV[9:0] to all zeros. Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on recommended PMS values. SDIV[2:0] controls division ratio of Scaler as described in Table 5-15. Table 5-15 lists the Division Ratio of Scaler. Table 5-15 Division Ratio of Scaler S[2:0] Division Ratio 000 2^0 = 1 001 2^1 = 2 010 2^2 = 4 011 2^3 = 8 100 2^4 = 16 101 2^5 = 32 110 Prohibited 111 Prohibited Refer to 5.3.2 Recommended PLL PMS Value for EPLL for more information on recommended PMS values.
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-51 5.9.1.3 APLL_CON1 Base Address: 0x1001_0000 Address = Base Address + 0x0104, Reset Value = 0x0020_3800 Name Bit Type Description Reset Value RSVD [31:22] –=Reserved=0x0= DCC_ENB=[21]=RW= Enables Duty Cycle Corrector (DCC)= (only for monitoring)= 0 = Enables DCC= 1 = Disables DCC= 0x1= AFC_ENB=x20]=RW= Decides=whether AFC is enabled or not (Active-= low)= 0 = Enables AFC= 1 = Disables AFC= 0x0= RSVD=x19:17]=–=Reserved=0x0= FEED_EN=[16]=RW=Enables=pin for FEED_OUT (Active-high)=0x0= LOCK_CON_OUT=[15:14]=RW=Lock detector setting of the output margin=0x0= LOCK_CON_IN=[13:12]=RW=Lock detector setting of the input margin=0x3= LOCK_CON_DLY=[11:8]=RW=Lock detector setting of the detection resolution=0x8= RSVD=[7:5]=–=Reserved=0x0= EXTAFC=[4:0]=RW=Enable pin for FVCO_OUT (Active-high)=0x0= = Adaptive=crequency=Calibrator=(AFC) automatically selects adaptive frequency curve of VCO using switched= current bank for:== Wide range High phase noise (or Jitter) Fast lock time Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL for more information on recommended AFC_ENB and EXTAFC values.
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-52 5.9.1.4 CLK_SRC_CPU Base Address: 0x1001_0000 Address = Base Address + 0x0200, Reset Value = 0x0000_0000; Name Bit Type Description Reset Value RSVD [31:21] –=Reserved=0x0= MUX_HPM_SEi=[20]=RW= Control MUu_HPM= 0 = MOUT_APLi= 1 = SCLK_MPLi= 0x0= RSVD=[19:17]=–=Reserved=0x0= MUX_CPr_SEL=[16]=RW= Control MUu_CPU= 0 = MOUT_APLi= 1 = SCLK_MPLi= 0x0= RSVD=[15:1]=–=Reserved=0x0= MUX_APLL_SEL=[0]=RW= Control MUu_APLL= 0 = XXTI= 1 = FOUT_APLi= 0x0= = 5.9.1.5 CLK_MUX_STAT_CPU Base Address: 0x1001_0000 Address = Base Address + 0x0400, Reset Value = 0x0011_0001 Name Bit Type Description Reset Value RSVD [31:23] –=Reserved=0x0= HPM_SEi=[22:20]=o= Selection signal status of MUXHPM= 001 = MOUT_APLi= 010 = SCLK_MPLi= 1xx===On changing= 0x1= RSVD=[19]=–=Reserved=0x0= CPU_SEL=[18:16]=o= Selection signal status of=MUX_CPU= 001 = MOUT_APLi= 010 = SCLK_MPLi= 1xx===On changing= 0x1= RSVD=[15:3]=–=Reserved=0x0= APLL_SEL=[2:0]=o= Selection signal status of=MUX_APLL= 001 = XXTI= 010 = FOUT_APLi= 1xx===On changing= 0x1= =
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-53 5.9.1.6 CLK_DIV_CPU0 Base Address: 0x1001_0000 Address = Base Address + 0x0500, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31] –=Reserved=0x0= ARM2_RATIO=[30:28]=RW=DIV_ARM2=clock divider Ratio= ARMCLK== DOUT_ARM/(ARM2_RATIO + 1)=0x0= RSVD=[27]=–=Reserved=0x0= APLL_RATIO=[26:24]=RW=DIV_APLL clock divider Ratio= SCLK_APLi== MOUT_APLL/(APLL_RATIO + 1)=0x0= RSVD=[23]=–=Reserved=0x0= PCLK_DBG= _RATIO=[22:20]=RW=DIV_PCLK_DBG clock divider Ratio= PCLK_DBG = ATCLK/(PCLK_DBG_RATIO + 1)=0x0= RSVD=[19]=–=Reserved=0x0= ATB_RATIl=[18:16]=RW= DIV_ATB clock divider Ratio= ATCLhEN ratio= =>=ARMCLK/(ATB_RATIO + 1)= 0x0= RSVD=[15]=–=Reserved=0x0= PERIPH_RATIO=[14:12]=RW= DIV_PERIPH clock divider Ratio= PERIPHCLhEN ratio= =>=ARMCLK/(PERIPH_RATIO + 1)= 0x0= RSVD=[11]=–=Reserved=0x0= ACP_RATIl=[10:8]=RW= DIV_ACm=clock divider Ratio= ACLKENS ratio= =>=ARMCLK/(ACm_RATIO + 1)= 0x0= RSVD=[7]=–=Reserved=0x0= CPUD_RATIO=[6:4]=RW=DIV_CPUa=clock divider Ratio= ACLK_CPUD== ARMCLK/(CPUD_RATIO + 1)=0x0= RSVD=[3]=–=Reserved=0x0= ARM_RATIO=x2:0]=RWu=DIV_ARM=clock divider Ratio= DOUT_ARM== MOUT_ARM/(ARM_RATIO + 1)=0x0= = =
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-54 5.9.1.7 CLK_DIV_CPU1 Base Address: 0x1001_0000 Address = Base Address + 0x0504, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:7] –=Reserved=0x0= HPM_RATIl=[6:4]=RW=DIV_HPM clock divider Ratio= SCLK_HPM = DOUT_COPY/(HPM_RATIO + 1)=0x0= RSVD=[3]=–=Reserved=0x0= COPY_RATIO=[2:0]=RWu=DIV_COPY clock divider Ratio= DOUT_COPY = MOUT_HPM/(COPY_RATIO + 1)=0x0= = =