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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-85  
5.9.1.56 CLK_DIV_SYSLFT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8900, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:12] –=Reserved=0x0=
EFCLK_SYSLFT_R
ATIO=x11:8]=RW=
SYSLFT EFCLK clock divider ratio,=
EFCLK_SYSLFT = SCLK_MPLL/ 
(EFCLK_SYSLFT_RATIO + 1)=
0x0=
RSVD=[7]=–=Reserved=0x0=
PCLK_SYSLFT_o
ATIO=x6:4]=RW=
SYSLFT PCLK clock divider ratio,=
PCLK_SYSLFT = ACLK_SYSLFT/=
(PCLK_SYSLFT_RATIO + 1)=
0x0=
RSVD=[3]=–=Reserved=0x0=
ACLK_SYSLFT_o
ATIO=x2:0]]=RW=
SYSLFT ACLK clock divider ratio,=
ACLK_SYSLFT = SCLK_MPLL/=
(ACLK_SYSLFT_RATIO + 1)=
0x0=
=
5.9.1.57 CLK_DIV_STAT_SYSLFT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8910, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
DIV_EFCLh=
_SYSLFT=x8]=o=
DIV_EFCLK_SYSLFT=status=
0 = Stable=
1 = Divider is on changing=
0x0=
RSVD=[7:5]=–=Reserved=0x0=
DIV_PCLK=
_SYSLFT=x4]=o=
DIV_PCLK_SYSLFT=status=
0 = Stable=
1 = Divider is on changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_ACLK=
_SYSLFT=x0]=o=
DIV_ACLK_SYSLFT=status=
0 = Stable=
1 = Divider is on changing=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-86  
5.9.1.58 CLK_GATE_BUS_SYSLFT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8920, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x7FFF=
EFCLh=x16]=ot=
Gating EFCLK clock for UFMC=
0 = Masks=
1 = Passes=
0x1=
RSVD=x15:0]=–=Reserved=0xFFFF=
=
5.9.1.59 CLK_GATE_IP_SYSLFT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8930, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x7FFF_FFFc=
CLK_SFRCDREXm
1=x0]=RW=
Gating all=Clocks for SFRCDREXP1=
0 = Masks=
1 = Passes=
0x1=
=
5.9.1.60 CLKOUT_CMU_ACP 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable=CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = SCLK_MPLi_LFT=
00001 = ACLK_ACP=
00010 = PCLK_ACP=
00011 = ACLK_SYSLFT=
00100== PCLK_SYSLFT=
00101 = EFCLK_SYSLFT=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-87  
5.9.1.61 CLKOUT_CMU_ACP_DIV_STAT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.62 UFMC_CONFIG 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8A10, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
SFMC_MODb=[0]=ot=
SFMC mode=selection=
0 = EF_NFCON=
1 = SFMC=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-88  
5.9.1.63 CLK_DIV_ISP0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC300, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0x0=
ISPDIV1_RATIO=[6:4]=RW=ACLK_DIV1=clock Divider Ratio=
ACLK_DIV1== ACLK_ISP/(ISPDIV1_RATIO + 1)=0x0=
RSVD=[3]=–=Reserved=0x0=
ISPDIV0_RATIO=[2:0]=RW=ACLK_DIV0=clock Divider ratio=
ACLK_DIV0== ACLK_ISP/(ISPDIV0_RATIO + 1)=0x0=
=
5.9.1.64 CLK_DIV_ISP1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC304, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0x0=
MCUISPDIV1=
_RATIO=[6:4]=RW=
PCLKDBG_MCUISP=clock Divider Ratio=
PCLKDBG_MCUISP== 
ATCLK_MCUISP/(MCUISPDIV1_RATIO + 1)=
0x0=
RSVD=[3]=–=Reserved=0x0=
MCUISPDIV0=
_RATIO=[2:0]=RW=
ATCLK_MCUISm=clock Divider Ratio=
ATCLK_MCUISm== 
ACLK_MCUISm/(MCUISPDIV0_RATIO + 1)=
0x0=
=
5.9.1.65 CLK_DIV_ISP2 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC308, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:3] –=Reserved=0x0=
MPWMDIs_RATIO=[2:0]=RW=
SCLK_MPWM_ISm=clock Divider Ratio=
SCLK_MPWM_ISm== 
ACLK_DIV1/(MPWMDIV_RATIO + 1)=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-89  
5.9.1.66 CLK_DIV_STAT_ISP0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC400, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
DIV_ISPDIV1=[4]=o=
DIV_ISPDIV1=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_ISPDIV0=[0]=o=
DIV_ISPDIV0=status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.67 CLK_DIV_STAT_ISP1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC404, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
DIV_MCUISPDIV1=[4]=o=
DIV_MCUISPDIV1=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_MCUISPDIV0=[0]=o=
DIV_MCUISPDIV0=status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.68 CLK_DIV_STAT_ISP2 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC408, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_MPWMIDs=[0]=o=
DIV_MPWMDIs=status=
0 = Stable=
1== Divider is changing=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-90  
5.9.1.69 CLK_GATE_IP_ISP0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC800, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
CLK_UART_ISP [31] RW 
Gating all Clocks for UART_ISP 
0 = Masks 
1 = Passes 
0x1 
CLK_WDT_ISP [30] RW 
Gating all Clocks for WDT_ISP 
0 = Masks 
1 = Passes 
0x1 
RSVD [29] –=Reserved=0x1=
CLK_PWM_ISm=[28]=RW=
Gating all=Clocks for PWM_ISm=
0 = Masks=
1 = Passes=
0x1=
CLK_MTCADC=
_ISP=[27]=RW=
Gating all=Clocks for MTCADC_ISP=
0 = Masks=
1 = Passes=
0x1=
CLK_I2C1_ISP=[26]=RW=
Gating all=Clocks for I2C1_ISP=
0 = Masks=
1 = Passes=
0x1=
CLK_I2C0_ISP=[25]=RW=
Gating all=Clocks for I2C0_ISP=
0 = Masks=
1 = Passes=
0x1=
CLK_MPt M_ISm=[24]=RW=
Gating all=Clocks for MPWM_ISP=
0 = Masks=
1 = Passes=
0x1=
CLK_MCUCTL=
_ISP=[23]=RW=
Gating all=Clocks for MCUCTL_ISP=
0 = Masks=
1 = Passes=
0x1=
CLK_INT_COMB=
_ISP=[22]=RW=
Gating all=Clocks for INT_COMB_ISP=
0 = Masks=
1 = Passes=
0x1=
RSVD=x21:14]=–=Reserved=0xFF=
CLK_SMMU=
_MCUISm=[13]=RW=
Gating all=Clocks for SMMU_MCUISm=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMU=
_SCALERP=[12]=RW=
Gating all=Clocks for SMMU_SCALERP=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMU=
_SCALERC=[11]=RW=
Gating all=Clocks for SMMU_SCALERC=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMU_Fa=[10]=RW=Gating all=Clocks for SMMU_Fa=0x1=
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Exynos 5250_UM 5 Clock Controller 
 5-91  
Name Bit Type Description Reset Value 
0 = Masks 
1 = Passes 
CLK_SMMU_DRC [9] RW 
Gating all Clocks for SMMU_DRC 
0 = Masks 
1 = Passes 
0x1 
CLK_SMMU_ISP [8] RW 
Gating all Clocks for SMMU_ISP 
0 = Masks 
1 = Passes 
0x1 
CLK_GICISP [7] RW 
Gating all Clocks for GICISP 
0 = Masks 
1 = Passes 
0x1 
CLK_ARM9S 
_MICE [6] RW 
Gating all Clocks for ARM9S_MICE 
0 = Masks 
1 = Passes 
0x1 
CLK_MCUISP [5] RW 
Gating all Clocks for MCUISP 
0 = Masks 
1 = Passes 
0x1 
CLK_SCALERP [4] RW 
Gating all Clocks for SCALERP 
0 = Masks 
1 = Passes 
0x1 
CLK_SCALERC [3] RW 
Gating all Clocks for SCALERC 
0 = Masks 
1 = Passes 
0x1 
CLK_FD [2] RW 
Gating all Clocks for FD 
0 = Masks 
1 = Passes 
0x1 
CLK_DRC [1] RW 
Gating all Clocks for DRC 
0 = Masks 
1 = Passes 
0x1 
CLK_ISP [0] RW 
Gating all Clocks for ISP 
0 = Masks 
1 = Passes 
0x1
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Exynos 5250_UM 5 Clock Controller 
 5-92  
5.9.1.70 CLK_GATE_IP_ISP1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC804, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:14] RW Reserved 0x3_FFFF 
CLK_SPI1_ISP [13] RW 
Gating all Clocks for SPI1_ISP 
0 = Masks 
1 = Passes 
0x1 
CLK_SPI0_ISP [12] RW 
Gating all Clocks for SPI0_ISP 
0 = Masks 
1 = Passes 
0x1 
RSVD [11:8] –=Reserved=0xc=
CLK_SMMU3DNR=x7]=RW=
Gating all=Clocks for=SMMU3DNR=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUDIS1=xS]=RW=
Gating all=Clocks for=SMMUDIS1=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUDIS0=x5]=RW=
Gating all=Clocks for=SMMUDIS0=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUODC=x4]=RW=
Gating all=Clocks for=SMMUODC=
0 = Masks=
1 = Passes=
0x1=
RSVD=x3]=RW=Reserved=0x1=
CLK_3DNR=x2]=RW=
Gating all=Clocks for=3DNR=
0 = Masks=
1 = Passes=
0x1=
CLK_DIp=x1]=RW=
Gating all=Clocks for=DIp=
0 = Masks=
1 = Passes=
0x1=
CLK_ODC=x0]=RW=
Gating all=Clocks for=ODC=
0 = Masks=
1 = Passes=
0x1=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-93  
5.9.1.71 CLK_GATE_SCLK_ISP 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC900, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:1] RW Reserved 0x7FFF_FFFF 
SCLK_MPWM_ISP [0] RW 
Gating Special Clocks for MPWM_ISP 
0 = Masks 
1 = Passes 
0x1 
 
5.9.1.72 MCUISP_PWR_CTRL 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC910, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] RW Reserved 0x7FFF_FFFF 
CSCLK_AUTO 
_ENB_IN_DEBUG [0] RW 
Force CoreSight Clocks to toggle when debugger 
is attached. 
0 = Disables 
1 = Enables 
0x0
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Exynos 5250_UM 5 Clock Controller 
 5-94  
5.9.1.73 CLKOUT_CMU_ISP 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xCA00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = ACLK_266 
00001 = ACLK_DIV0 
00010 = ACLK_DIV1 
00011 = SCLK_MPW M_ISP 
0x0 
 
5.9.1.74 CLKOUT_CMU_ISP_DIV_STAT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xCA04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT Status=
0 = Stable=
1 = Divider is=changing=
0x0=
=
=
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