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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-277  
Name Bit Type Description Reset Value 
_CON[2] 0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
RSVD [7] – Reserved 0x0 
EXT_INT61 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT61[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT61 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT61[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-278  
4.4.1.407 EXT_INT62CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0708, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
EXT_INT62=
_CON[7]=[30:28]=RW=
Setting the signaling method=of EXT_INT62[7]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT62=
_CON[6]=[26:24]=RW=
Setting the signaling method=of=EXT_INT62[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[23]=–=Reserved=0x0=
EXT_INT62=
_CON[5]=[22:20]=RW=
Setting the signaling method=of=EXT_INT62[5]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[19]=–=Reserved=0x0=
EXT_INT62=
_CON[4]=[18:16]=RW=
Setting the signaling method=of=EXT_INT62[4]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[15]=–=Reserved=0x0=
EXT_INT62=
_CON[3]=[14:12]=RW=
Setting the signaling method=of EXT_INT62[3]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[11]=–=Reserved=0x0=
EXT_INT62=[10:8]=RW=Setting the signaling method=of=EXT_INT62[2]=0x0=
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-279  
Name Bit Type Description Reset Value 
_CON[2] 0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
RSVD [7] – Reserved 0x0 
EXT_INT62 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT62[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT62 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT62[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0
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Exynos 5250_UM 4 Pad Control 
 4-280  
4.4.1.408 EXT_INT63CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x070C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
EXT_INT63=
_CON[7]=[30:28]=RW=
Setting the signaling method=of EXT_INT63[7]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT63=
_CON[6]=[26:24]=RW=
Setting the signaling method=of EXT_INT63[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[23]=–=Reserved=0x0=
EXT_INT63=
_CON[5]=[22:20]=RW=
Setting the signaling method=of EXT_INT63[5]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[19]=–=Reserved=0x0=
EXT_INT63=
_CON[4]=[18:16]=RW=
Setting the signaling method=of EXT_INT63[4]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[15]=–=Reserved=0x0=
EXT_INT63=
_CON[3]=[14:12]=RW=
Setting the signaling method=of EXT_INT63[3]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3== Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[11]=–=Reserved=0x0=
EXT_INT63=[10:8]=RW=Setting the signaling method=of EXT_INT63[2]=0x0=
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-281  
Name Bit Type Description Reset Value 
_CON[2] 0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
RSVD [7] – Reserved 0x0 
EXT_INT63 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT63[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT63 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT63[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0
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Exynos 5250_UM 4 Pad Control 
 4-282  
4.4.1.409 EXT_INT64CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0710, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x000000=
RSVD=[7]=–=Reserved=0x0=
EXT_INT64=
_CON[1]=[6:4]=RW=
Setting the signaling method=of EXT_INT64[1]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[3]=–=Reserved=0x0=
EXT_INT64=
_CON[0]=[2:0]=RW=
Setting the signaling method=of EXT_INT64[0]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to=0x7 = Reserved=
0x0=
=
=
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-283  
4.4.1.410 EXT_INT60_FLTCON0 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0800, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN1[3] [31] RW 
Enables Filter for EXT_INT60[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[3] [30:24] RW Filtering width of EXT_INT60[3] 0x00 
FLTEN1[2] [23] RW 
Enables Filter for EXT_INT60[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[2] [22:16] RW Filtering width of EXT_INT60[2] 0x00 
FLTEN1[1] [15] RW 
Enables Filter for EXT_INT60[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[1] [14:8] RW Filtering width of EXT_INT60[1] 0x00 
FLTEN1[0] [7] RW 
Enables Filter for EXT_INT60[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[0] [6:0] RW Filtering width of EXT_INT60[0] 0x00
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-284  
4.4.1.411 EXT_INT60_FLTCON1 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0804, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN1[7] [31] RW 
Enables Filter for EXT_INT60[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[7] [30:24] RW Filtering width of EXT_INT60[7] 0x00 
FLTEN1[6] [23] RW 
Enables Filter for EXT_INT60[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[6] [22:16] RW Filtering width of EXT_INT60[6] 0x00 
FLTEN1[5] [15] RW 
Enables Filter for EXT_INT60[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[5] [14:8] RW Filtering width of EXT_INT60[5] 0x00 
FLTEN1[4] [7] RW 
Enables Filter for EXT_INT60[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[4] [6:0] RW Filtering width of EXT_INT60[4] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-285  
4.4.1.412 EXT_INT61_FLTCON0 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0808, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN2[3] [31] RW 
Enables Filter for EXT_INT61[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[3] [30:24] RW Filtering width of EXT_INT61[3] 0x00 
FLTEN2[2] [23] RW 
Enables Filter for EXT_INT61[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[2] [22:16] RW Filtering width of EXT_INT61[2] 0x00 
FLTEN2[1] [15] RW 
Enables Filter for EXT_INT61[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[1] [14:8] RW Filtering width of EXT_INT61[1] 0x00 
FLTEN2[0] [7] RW 
Enables Filter for EXT_INT61[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[0] [6:0] RW Filtering width of EXT_INT61[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-286  
4.4.1.413 EXT_INT61_FLTCON1 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x080C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN2[7] [31] RW 
Enables Filter for EXT_INT61[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[7] [30:24] RW Filtering width of EXT_INT61[7] 0x00 
FLTEN2[6] [23] RW 
Enables Filter for EXT_INT61[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[6] [22:16] RW Filtering width of EXT_INT61[6] 0x00 
FLTEN2[5] [15] RW 
Enables Filter for EXT_INT61[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[5] [14:8] RW Filtering width of EXT_INT61[5] 0x00 
FLTEN2[4] [7] RW 
Enables Filter for EXT_INT61[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH2[4] [6:0] RW Filtering width of EXT_INT61[4] 0x00
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