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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-155  
5.9.1.142 CLK_DIV_STAT_PERIC1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x065C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x0=
DIV_SPI1_PRE=[24]=o=
DIV_SPI1_PRE status=
0 = Stable=
1 ==Divider is changing=
0x0=
RSVD=[23:17]=–=Reserved=0x0=
DIV_SPI1=[16]=o=
DIV_SPI1 status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[15:9]=–=Reserved=0x0=
DIV_SPI0_PRE=[8]=o=
DIV_SPI0_PRE status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[7:1]=–=Reserved=0x0=
DIV_SPI0=[0]=o=
DIV_SPI0 status=
0 = Stable=
1 = Divider is=changing=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-156  
5.9.1.143 CLK_DIV_STAT_PERIC2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0660, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
DIV_SPI2_PRE=[8]=o=
DIV_SPI2_PRE status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[7:1]=–=Reserved=0x0=
DIV_SPI2=[0]=o=
DIV_SPI2=status=
0 = Stable=
1 = Divider is=changing=
0x0=
=
5.9.1.144 CLK_DIV_STAT_PERIC3 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0664, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_PWM=[4]=o=
DIV_PWM=status=
0 = Stable=
1 = Divider is changing=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-157  
5.9.1.145 CLK_DIV_STAT_PERIC4 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0668, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x0=
DIV_PCM2=[20]=o=
DIV_PCM2 status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
DIV_AUDIO2=[16]=o=
DIV_AUDIO2 status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[15:5]=–=Reserved=0x0=
DIV_PCM1=[4]=o=
DIV_PCM1 status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_AUDIO1=[0]=o=
DIV_AUDIO1 status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.146 CLK_DIV_STAT_PERIC5 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x066C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
DIs_I2S2=[8]=o=
DIV_I2S2 status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[7:1]=–=Reserved=0x0=
DIV_I2S1=[0]=o=
DIV_I2S1 status=
0 = Stable=
1 = Divider is=changing=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-158  
5.9.1.147 SCLK_DIV_STAT_ISP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0680, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x0=
DIV_PWM_ISm=x20]=o=
DIV_PWM_ISm=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x19:17]=–=Reserved=0x0=
DIV_UART_ISP=x16]=o=
DIV_UART_ISP=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x15:13]=–=Reserved=0x0=
DIV_SPI1_ISP=
_PRE=x12]=o=
DIV_SPI1_ISP_PRE=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x11:9]=–=Reserved=0x0=
DIV_SPI1_ISP=x8]=o=
DIV_SPI1_ISP=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x7:5]=–=Reserved=0x0=
DIV_SPf0_ISP=
_PRE=x4]=o=
DIV_SPI0_ISP_PRE=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x3:1]=–=Reserved=0x0=
DIV_SPI0_ISP=x0]=o=
DIV_SPI0_ISP=status=
0 = Stable=
1 = Divider is=changing=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-159  
5.9.1.148 CLKDIV2_STAT0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0690, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x0=
JPGX_DIs=[20]=o=
PCLK divider status in=JPGX_DIV=(GEN_BLK)=
0 = Stable=
1 = Divider is=changing=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
DISP1_BLh=[16]=o=
PCLK divider status in=DISP1_BLh=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[15:9]=–=Reserved=0x0=
GEN_BLK=[8]=o=
PCLK divider status in=GEN_BLK=
0 = Stable=
1 ==Divider is changing=
0x0=
RSVD=[7:5]=–=Reserved=0x0=
GSCL_BLK=[4]=o=
PCLK divider status in=GSCL_BLK=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-160  
5.9.1.149 CLKDIV2_STAT1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0694, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
G3D_BLK_PCLK=x8]=o=
PCLK divider status in=G3a_BLK=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x7:5]=–=Reserved=0x0=
FSYS_PCLKDBG=[4]=o=
PCLKDBd=divider status in FSYS_BLK=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
FSYS_ATCLK=x0]=o=
ATCLh=divider status in FSYS_BLK=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.150 CLKDIV4_STAT 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x06A0, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
MFC_BLh=x0]=o=
PCLK divider status in=MFC_BLK=
0 = Stable=
1 = Divider is changing=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-161  
5.9.1.151 CLK_GATE_TOP_SCLK_DISP1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0828, Reset Value = 0XFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
5.9.1.152 CLK_GATE_TOP_SCLK_GEN 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x082C, Reset Value = 0XFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
5.9.1.153 CLK_GATE_TOP_SCLK_MAU 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x083C, Reset Value = 0XFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-162  
5.9.1.154 CLK_GATE_TOP_SCLK_FSYS 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0840, Reset Value = 0XFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
5.9.1.155 CLK_GATE_TOP_SCLK_PERIC 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0850, Reset Value = 0XFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
5.9.1.156 CLK_GATE_TOP_SCLK_ISP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0870, Reset Value = 0XFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-163  
5.9.1.157 CLK_GATE_IP_GSCL 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0920, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x7Fc=
CLK_SMMUFIMC=
_LITE2=x20]=RW=
Gating all Clocks for SMMUFIMC_LITE2=
0 = Masks=
1 = Passes=
0x1=
RSVD=x19:13]=–=Reserved=0x7F=
CLK_SMMUFIMC=
_LITE1=[12]=RW=
Gating all Clocks for SMMUFIMC_LITE1=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUFIMC=
_LITE0=[11]=RW=
Gating all Clocks for SMMUFIMC_LITE0=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUGSCL3=[10]=RW=
Gating all Clocks for SMMUGSCL3=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUGSCL2=[9]=RW=
Gating all Clocks for SMMUGSCL2=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUGSCL1=[8]=RW=
Gating all=Clocks for SMMrGSCL1=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUGSCL0=[7]=RW=
Gating all Clocks for SMMUGSCL0=
0 = Masks=
1 = Passes=
0x1=
CLK_GSCL=
_WRAP_B=[6]=RW=
Gating all Clocks for GSCL_WRAP_B=
0 = Masks=
1 = Passes=
0x1=
CLK_GSCL=
_WRAP_A=[5]=RW=
Gating all Clocks for GSCL_WRAP_A=
0 = Masks=
1 ==Passes=
0x1=
CLK_CAMIF_TOm=[4]=RW=Gating all Clocks for CAMIF_TOm=0x1=
CLK_GSCL3=[3]=RW=
Gating all Clocks for GSCL3=
0 = Masks=
1 = Passes=
0x1=
CLK_GSCL2=[2]=RW=
Gating all Clocks for GSCL2=
0 = Masks=
1 = Passes=
0x1=
CLK_GSCL1=[1]=RW=
Gating all Clocks for GSCL1=
0 = Masks=
1 = Passes=
0x1=
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Exynos 5250_UM 5 Clock Controller 
 5-164  
Name Bit Type Description Reset Value 
CLK_GSCL0 [0] RW 
Gating all Clocks for GSCL0 
0 = Masks 
1 = Passes 
0x1
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