Samsung Exynos 5 User Manual
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Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-15
Figure 5-3 Exynos 5250 Clock Generation Circuit (CPU, BUS, DRAM Clocks) 2 CMU_TOP
EPLL(PLL3600)
0
1
DPTX_PHYSCLK_DPTXPHY
SCLKEPLL
MUXEPLL
MUXVPLL
FOUTEPLL
FOUTVPLL
0
1MOUTACLK_300_DISP1_MID
MUXACLK_300_DISP1_MID
ACLK_300_DISP1DIVACLK_300_DISP1(1~8) /1
USB_HOST20_PHYSCLK_UHOSTPHY
DIVACLK_200(1~8) /4
DIVACLK_266(1~8) /3
ACLK_266
G3D_BLK
CMU_ISP
ACLK_ISP
DIVISPDIV0(1~8) /2
ACLK_DIV0
MAU_BLK
MFC_BLK
GEN_BLK (JPGX_DIV)
LEX_BLKRIX_BLKACP_BLKGEN_BLK
DIVACLK_66(1~8) /2
ACLK_66PERIS_BLKPERIC_BLK
CPLL(PLL3500)
0
1
SCLKMPLL
0
1
MOUTACLK_333
MUXACLK_333
DIVACLK_333(1~8) /1
DIVACLK_166(1~8) /2
ACLK_166
FOUTCPLL
MUXCPLL
ACLK_266_ISP
200MHz
DIVISPDIV1(1~8) /4
DIVMPWMIV(1~8) /1
ACLK_DIV1
SCLK_MPWM_ISP
0
1
MUXACLK_166
0
1
MUXACLK_200
MOUTACLK_200
SCLKBPLL
DIVACLK_400_IOP(1~8) /2
ACLK_400_IOPFSYS_BLK(Cortex-A5)
0
1
MOUTACLK_400_IOP
DIVACLK_66_pre(1~8) /6
DIVACLK_400_ISP(1~8) /2
ISP_BLK(Cortex-A5)0
1
MUXACLK_400_ISP
MOUTACLK400_ISP
DIVACLK_MIPI_HSI_TXBASE(1~8)
ACLK_MIPI_HSI_TXBASEFSYS_BLK(MPI_HIS)
0
1
MUXACLK_MIPI_HSI_TXBASE
MOUTACLK_MIPI_HSI_TXBASE
MUXACLK_400_IOP
0
1
MUXBPLL_USER
MOUTBPLL_USER
0
1
MUXMPLL_USER
MOUTMPLL_USER
PLL_USER muxes are
necessary to switch PLL
clocks to XXTI when C2C
interface is supposed to
run in SLEEP mode.
OSCCLK
DISP1_BLK
FSYS_BLK
ACLK_200_DISP10
1
MOUTACLK_200_DISP1_SUB
MUXACLK_200_DISP1_SUB
ACLK_200
ACLK_400_ISP0
1
MOUTACLK_400_ISP_SUB
MUXACLK_400_ISP_SUBOSCCLK
0
1
MUXACLK_333_SUB
MOUTACLK_333_SUB
ACLK_333
ACLK_266_GSCL0
1
MOUTACLK_266_GSCL_SUB
MUXACLK_266_GSCL_SUBOSCCLK
MOUTACLK_266_GPS_SUB
SUB glitch-free mux is used to switch
normal operating clock to OSCCLK to
prevent timing violations due to
default clock divider setting in sub-
block after wakeup from power gating.
GSCL_BLK
ISP_BLKACLK_266_ISP0
1
MOUTACLK_266_ISP_SUB
MUXACLK_266_ISP_SUB
ACLK_MCUISP
DIVMCUISPDIV0(1~8) /2
ATCLK_MCUISP
ACLK_400_ISP
DIVMCUISPDIV1(1~8) /4
PCLKDBG_MCUISP
0
1DIVACLK_400_G3D(1~8) /1
ACLK_400_G3D
MUXACLK_400_G3D_MID
MOUTACLK_400_G3D_MID
0
1
MUXACLK_300_DISP1_SUB
0
1
MUXVPLL_USER
0
1
MOUTACLK_300_GSCL_SUB
MUXACLK_300_GSCL_SUB
DIVACLK_300_GSCL(1~8) /1
0
1
MUXACLK_300_GSCL_MID
MOUTACLK_300_GSCL_MID
GSCL_BLK
MUXACLK_300_DISP1
MOUTACLK_300_DISP1
ACLK_300_GSCL(SCLK_GSCALER)
0
1
MUXACLK_300_GSCL
MOUTACLK_300_GSCL
MOUTACLK_300_DISP1_SUB
DISP1_BLK
USB20_XI
XdpOSC24M
0
1
GPLL(PLL3500)
0
1
FOUTGPLL
MUXGPLL
MOUTACLK_400_G3D
MUXACLK_400_G3D
CMU_R0X
ACLK_PR0XDIVPR0X(1~8)(2)
ACLK_DR0XACLK_266
CMU_R1X
ACLK_PR1XDIVPR1X(1~8)(2)
ACLK_DR1XACLK_266
CMU_LEX
PCLK_LEXDIVPCLK_LEX(1~8) (2)
ACLK_DLEXACLK_266
ATCLK_LEXACLK_200
DIVATCLK_LEX(1~8)(1)
266MHz266MHz
133MHz
66MHz
66MHz
133MHz
66MHz
66MHz
400MHz400MHz
200MHz
100MHz
200MHz
100MHz
533MHz
533MHz
533MHz
800MHz
800MHz
300MHz
533MHz
333MHz333MHz
200MHz800MHz
333MHz
333MHz
800MHz
800MHz
800MHz
333MHz(1GHz, STA)
333MHz(1GHz, STA)
333MHz(1GHz, STA)
333MHz166MHz
333MHz
800MHz
800MHz
133MHz66MHz
266MHz
400MHz
400MHz
200MHz
333MHz
200MHz
333MHz
400MHz
333MHz
266MHz
266MHz
0
1ACLK_266
266MHz
133MHz
266MHz
133MHz
200MHz
266MHz
133MHz
0
1MOUTACLK_300_DISP1_MID1
MUXACLK_300_DISP1_MID1
0
1
MUXACLK_300_GSCL_MID1
MOUTACLK_300_GSCL_MID1333MHz
333MHz
VPLL(PLL3600)
0
10
1SCLK_HDMI24M
MUXVPLL_SRCLK
XXTI
SCLKBPLL_USER
SCLKMPLL_USER
MUXATCLK_LEX
MOUTATCLK_LEX
MOUTVPLL
MOUTGPLL
MOUTCPLL
MOUTEPLL
MOUTVPLL_SRCLK
SCLKVPLL
SCLKCPLL
SCLKGPLL
HDMI_PHY
SCLK_HDMIPHY
SCLK_HDMI24MXhdmiXTI
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-16
Figure 5-4 and Figure 5-5 illustrate the Exynos 5250 clock generation circuit (special clocks)
Figure 5-4 Exynos 5250 Clock Generation Circuit (Special Clocks) 1
MUXMMC0~3
MOUTMMC0~3
FSYS_BLK
SCLK_MMC0~3DIVMMC0~3(1~16)DIVMMC0~3_PRE(1~256)
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKVPLLSCLKCPLL
GEN_BLK
SCLKMPLL_USER
SCLKCPLL
0
1DIVUSBDRD30(1~16)
SCLK_USBRD30
MOUTUSBDRD30
ISP_BLK
DIVPWM_ISP(1~16)
SCLK_PWM_ISP
MUXPWM_ISP
MOUTPWM_ISP
DIVUART_ISP(1~16)
SCLK_UART_ISP
MUXUART_ISP
MOUTUART_ISP
DIVSPI1_ISP(1~16)
SCLK_SPI1_ISP
MUXSPI1_ISP
MOUTSPI1_ISP
DIVSPI1_ISP_PRE(1~256)
DIVSPI0_ISP(1~16)
SCLK_SPI0_ISP
MUXSPI0_ISP
MOUTSPI0_ISP
DIVSPI0_ISP_PRE(1~256)
SCLKMPLL_USER
DIVCAM0,1,BAYER(1~16)
SCLK_CAM0,1,BAYER (PAD)
MUXCAM0,1,BAYER
MOUTCAM0,1,BAYER
DIVGSCL_WRAPA,B(1~16)
SCLK_GSCL_WRAPA,B
MUXGSCL_WRAPA,B
MOUTGSCL_WRAPA,B
GSCL_BLK
XXTIXXTISCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
SCLKMPLL_USER
SCLKBPLL_USER
0
1DIVSATA(1~16)
SCLK_SATA
MOUTSATA
SCLKGPLL
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
DIVJPEG(1~16)
SCLK_JPEG
MOUTJPEG
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
SCLKBPLL_USER
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-17
Figure 5-5 Exynos 5250 Clock Generation Circuit (Special Clocks) 2
Caution: In Figure 5-2 and Figure 5-5, muxes with grey color are glitch-free. For glitch-free clock muxes,
ensure that all clock sources are running when clock selection is changed.
For clock dividers, ensure that input clock is running when divider value is changed DIVAUDIO0(1~16)
SCLK_AUDIO0
MUXAUDIO0
DIVAUDIO1(1~16)
SCLK_AUDIO1
MUXAUDIO1
DIVAUDIO2(1~16)
SCLK_AUDIO2
MUXAUDIO2
MOUTAUDIO0
MOUTAUDIO1
MOUTAUDIO2
AUDIO_BLK
SCLK_HDMIDIVHDMI_PIXEL(1~16)
SCLKVPLL0
1SCLK_HDMIPHY
MUXHDMI
SCLK_PIXEL
DIVPCM0~2(1~256)
SCLK_PCM0~2SCLK_AUDIO0~2
SCLK_AUDIO0 SCLK_AUDIO1 SCLK_AUDIO2 SPDIF_EXTCLK
SCLK_SPDIFMUXSPDIF
DIVI2S1~2(1~64)
SCLK_I2S1~2SCLK_AUDIO1~2
DISP1_BLK
DIVFIMD1(1~16)
SCLK_FIMD1
MUXFIMD1
MOUTFIMCD1
DIVMIPI1(1~16)
SCLK_MIPI1
MUXMIPI1
MOUTMIPI1
DIVMIPI1_PRE(1~16)
SCLK_MIPIDPHY1
DIVEXT_MST_VID(1~16)
SCLK_DP1_EXT_MST_VID
MUXDP1_EXT_MST_VID
MOUTDP1_EXT_MST_VID
DIVSPI0~2(1~16)
SCLK_SPI0~2
DIVUART0~3(1~16)
SCLK_UART0~3
MUXSPI0~2
MUXUART0~3
MOUTUART0~3
MOUTSPI0~2
PERI_BLK
DIVSPI0~2_PRE(1~256)
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USER
XXTI
AUDIOCDCLK0 XXTISCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USERXXTI
AUDIOCDCLK0 XXTISCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USERXXTI
AUDIOCDCLK0 XXTISCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHY
SCLKEPLLSCLKVPLLSCLKCPLL
SCLKMPLL_USERXXTI
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-18 Table 5-5 through Table 5-10 show maximum input frequency for each clock divider. Dividers in CMU_CPU block need overdrive to divide 1700 MHz or 340 MHz (DIV_PCLK_DBG) input clocks. Table 5-5 Maximum Input Frequency for Clock Divider-1 Block Divider MAX Input Frequency (MHz) CMU_TOP DIV_CLKOUT 1000 DIV_ACLK_166 1000 DIV_ACLK_200 800 DIV_ACLK_266 800 DIV_ACLK_300_DISP1 800 DIV_ACLK_300_GSCL 800 DIV_ACLK_333 1000 DIV_ACLK_400_G3D 800 DIV_ACLK_400_IOP 800 DIV_ACLK_400_ISP 800 DIV_ACLK_66 133 DIV_ACLK_66_PRE 800 DIV_ACLK_MIPI_HSI_TXBASE 800 DIV_AUDIO0 200 DIV_AUDIO1 200 DIV_AUDIO2 200 DIV_CAM0 800 DIV_CAM1 800
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-19 Table 5-6 Maximum Input Frequency for Clock Divider-2 Block Divider MAX Input Frequency (MHz) CMU_TOP DIV_CAM_BAYER 800 DIV_DP1_EXT_MST_VID 900 DIV_FIMD1 900 DIV_GSCL_WRAP_A 800 DIV_GSCL_WRAP_B 800 DIV_HDMI_PIXEL 900 DIV_I2S1 100 DIV_I2S2 100 DIV_JPEG 333 DIV_MIPI1 920 DIV_MIPI1_PRE 115 DIV_MMC0 800 DIV_MMC0_PRE 800 DIV_MMC1 800 DIV_MMC1_PRE 800 DIV_MMC2 800 DIV_MMC2_PRE 800 DIV_MMC3 800 DIV_MMC3_PRE 800 DIV_PCM0 100 DIV_PCM1 100
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-20 Table 5-7 Maximum Input Frequency for Clock Divider-3 Block Divider MAX Input Frequency (MHz) CMU_TOP DIV_PCM2 100 DIV_PWM 800 DIV_PWM_ISP 800 DIV_SATA 800 DIV_SPI0 800 DIV_SPI0_ISP 800 DIV_SPI0_ISP_PRE 100 DIV_SPI0_PRE 100 DIV_SPI1 800 DIV_SPI1_ISP 800 DIV_SPI1_ISP_PRE 100 DIV_SPI1_PRE 100 DIV_SPI2 800 DIV_SPI2_PRE 100 DIV_UART0 800 DIV_UART1 800 DIV_UART2 800 DIV_UART3 800 DIV_UART_ISP 800 DIV_USBDRD30 800
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-21 Table 5-8 Maximum Input Frequency for Clock Divider-4 Block Divider MAX Input Frequency (MHz) CMU_CPU DIV_CLKOUT 1265 DIV_ACP (not used) 1700 DIV_APLL 1700 DIV_ARM 1700 DIV_ARM2 1700 DIV_ATB 1700 DIV_COPY 800 DIV_CPUD 1700 DIV_HPM 800 DIV_PCLK_DBG 340 DIV_PERIPH (not used) 1700 CMU_ISP DIV_CLKOUT 550 DIV_ISPDIV0 266 DIV_ISPDIV1 266 DIV_MPWMDIV 66 DIV_MCUISPDIV0 400 DIV_MCUISPDIV1 400 CMU_LEX DIV_CLKOUT 266 DIV_ATLEX 266 DIV_PLEX 266
Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-22 Table 5-9 Maximum Input Frequency for Clock Divider-5 Block Divider MAX Input Frequency (MHz) CMU_R0X DIV_CLKOUT 266 DIV_PR0X 266 CMU_R1X DIV_CLKOUT 266 DIV_PR1X 266 CMU_ACP DIV_CLKOUT 500 DIV_ACLK_ACP 800 DIV_PCLK_ACP 266 DIV_ACLK_SYSLFT 800 DIV_PCLK_SYSLFT 400 DIV_EFPHY_SYSLFT 800 CMU_CDREX DIV_CLKOUT 900 DIV_MCLK_CDREX 800 DIV_PCLK_CDREX 266 DIV_MCLK_CDREX2 800 DIV_ACLK_CDREX 800 DIV_ACLK_SFRTZASCP 400 DIV_MCLK_DPHY 800 CMU_CORE DIV_CLKOUT 750 DIV_CORED 800 DIV_COREP 266 Table 5-10 Maximum Input Frequency for Clock Divider-6 Block Divider MAX Input Frequency(MHz) CMU_CORE DIV_RSVD1_CORE 133 DIV_RSVD2_CORE 133 DIV_C2C_CLK_400 800 DIV_ACLK_C2C_200 400 DIV_ACLK_R1BX 800 DIV_RSVD3_CORE 800
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-23
5.5 Clock Configuration Procedure
You should follow these rules while changing clock configuration: You should run all inputs of a glitch-free
mux.
You should not select the output of PLL when a PLL is turned off.
Basic SFR Configuration Flows:
1. Change the system clock divider values as:
CLK_DIV_CPU0[31:0] = target value 0;
CLK_DIV_CORE0[31:0] = target value 1;
CLK_DIV_CDREX[31:0] = target value 2;
CLK_DIV_ACP[31:0] = target value 3;
CLK_DIV_ISP[31:0] = target value 4;
CLK_DIV_TOP[31:0] = target value 5;
CLK_DIV_LEX[31:0] = target value 6;
CLK_DIV_R0X[31:0] = target value 7;
CLK_DIV_R1X[31:0] = target value 8;
2. Change the divider values for special clocks by setting CLK_DIV_XXX SFRs in CMU_TOP
CLK_DIV_XXX[31:0] = target value;
3. Change PLL PMS values
Set PMS values:
// Set PDIV, MDIV, and SDIV values
(Refer to (A, M, B, C, E, G, V) PLL_CON0 SFRs for more
information)
4. Change other PLL control values
(A, M, B, C, E, G, V) PLL_CON1[31:0] = target value;
// Set K, AFC, MRR, and MFR values if necessary
(Refer to (A, M, B, C, E, G, V) PLL_CON1 SFRs for more
information)
Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-24
5. Turn on a PLL
(A, M, B, C, E, G, V) PLL_CON0[31] = 1;
// Turn on a PLL (Refer to (A, M, B, C, E, G, V) PLL_CON0 SFRs
for more information)
wait_lock_time;
// Wait until the PLL is locked
MUX_(A, M, B, C, E, G, V) PLL_SEL = 1;
// After PLL output clock is stabilized, select the PLL output
clock instead of input reference clock. (Refer to CLK_SRC_CPU
SFR for APLL, CLK_SRC_CORE1 SFR for MPLL,
CLK_SRC_CDREX for BPLL, and CLK_SRC_TOP2 for CPLL,
GPLL, EPLL and VPLL for more information) When a PLL is
turned on,do not turn it off.