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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-75  
5.9.1.41 CLK_DIV_CORE0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0x0=
COREm_RATIO=x22:20]=RW=
DIs_COREP=clock divider Ratio=
ACLK_COREm=
= ACLK_CORED/(COREm_RATIO + 1)=
0x0=
RSVD=x19]=–=Reserved=0x0=
COREa_RATIO=x18:16]=RW=
DIs_CORED=clock divider Ratio=
ACLK_COREa=
= MOUT_MPLi/(COREa_RATIO + 1)=
0x0=
RSVD=x15:0]=–=Reserved=0x0=
=
5.9.1.42 CLK_DIV_CORE1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4504, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
RSVD1_CORE_RA
TIl=x30:24]=RW=
DIs_RSVD1_CORb=clock divider Ratio=
SCLK_RSVD1_CORE== 
MOUT_RSVD1_CORb/(RSVD1_CORE_RATIO +=
1)=
0x0=
RSVD=x23]=–=Reserved=0x0=
RSVD2_CORE_RA
TIl=x22:16]=RW=
DIs_RSVD2_CORb=clock divider Ratio=
SCLK_RSVD2_CORE== 
MOUT_RSVD2_CORb/(RSVD2_CORE_RATIO +=
1)=
0x0=
RSVD=x15:12]=–=Reserved=0x0=
RSVD3_CORE_RA
TIl=x11:8]=RW=
DIs_RSVD3_CORb=clock divider Ratio=
SCLK_RSVD3_CORE== 
MOUT_RSVD3_CORb/(RSVD3_CORE_RATIO +=
1)=
0x0=
RSVD=x7:0]=–=Reserved=0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-76  
5.9.1.43 CLK_DIV_SYSRGT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4508, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:11] –=Reserved=0x0=
ACLK_C2C_200_R
ATIO=x10:8]=RW=
DIs_ACLK_C2C_200=clock divider Ratio.=
ACLK_C2C_200== 
C2C_CLK_400/(ACLK_C2C_200_=RATIO + 1)=
0x0=
RSVD=x7]=–=Reserved=0x0=
C2C_CLK_400=
_RATIO=xS:4]=RW=
DIV_C2C_CLK_400 clock divider ratio,=
C2C_CLK_400 = 
MUX_C2C_CLK_400_CLK/(C2C_CLK_400_RATI
O + 1)=
0x0=
RSVD=x3]=–=Reserved=0x0=
ACLK_R1Bu=
_RATIO=x2:0]=RW=
DIV_ACLK_R1BX=clock divider ratio,=
ACLK_R1BX== 
MOUT_ACLK_R1BX/(ACLK_R1BX_RATIO + 1)=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-77  
5.9.1.44 CLK_DIV_STAT_CORE0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x0=
DIV_COREm=x20]=o=
DIs_COREP=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x19:17]=–=Reserved=0x0=
DIV_COREa=x16]=o=
DIs_CORED=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x15:0]=–=Reserved=0x0=
=
5.9.1.45 CLK_DIV_STAT_CORE1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4604, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x0=
DIV_oSVD1_COR
b=x24]=–=
DIs_RSVD1_CORb=status=
0 = Stable=
1 = Divider is=changing=
0x0=
RSVD=x23:17]=–=Reserved=0x0=
DIV_RSVD2_COo
b=x16]=–=
DIs_RSVD2_CORb=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x15:9]=–=Reserved=0x0=
DIV_RSVD3_COo
b=x8]=–=
DIs_RSVD3_CORb=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x7:0]=–=Reserved=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-78  
5.9.1.46 CLK_DIV_STAT_SYSRGT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4608, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
DIV_ACLK_C2C_2
00=x8]=o=
DIs_ACLK_C2C_200=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x7:5]=–=Reserved=0x0=
DIV_C2C_CLh=
_400=x4]=o=
DIs_C2C_CLK_400=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=x3:1]=–=Reserved=0x0=
DIV_ACLK=
_R1BX=x0]=o=
DIV_ACLK_R1BX=status=
0 = Stable=
1 = Divider is=changing=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-79  
5.9.1.47 CLK_GATE_IP_CORE 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4900, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0xFF=
CLK_CoreMEM=[23]=RW=
Gating all=Clocks for=CoreMEM=
0 = Masks=
1 = Passes=
0x1=
CLK_ASYNC=
_ACPu=[22]=RW=
Gating all=Clocks for=ASYNC_ACPX=
0 = Masks=
1 = Passes=
0x1=
CLK_GIC_IOm=[21]=RW=
Gating all=Clocks for GIC_IOm=
0 = Masks=
1 = Passes=
0x1=
CLK_GIC_CPr=[20]=RW=
Gating all=Clocks for GIC_CPr=
0 = Masks=
1 = Passes=
0x1=
RSVD=x19]=–=Reserved=0x1=
oSVD_18=[18]=RW=Reserved=0x1=
oSVD_17=[17]=RW=Reserved=0x1=
RSVD=x16:4]=–=Reserved=0x3FFF=
CLK_INT_COMB=
_IOP=[3]=RW=
Gating all=Clocks for INT_COMB_IOP=
0 = Masks=
1 = Passes=
0x1=
CLK_INT_COMB=
_CPU=[2]=RW=
Gating all=Clocks for INT_COMB_CPU=
0 = Masks=
1 = Passes=
0x1=
RSVD=[1:0]=–=Reserved=0x3=
=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-80  
5.9.1.48 CLK_GATE_IP_SYSRGT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4904, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x3FFF_FFFF=
CLK_C2C=[1]=RW=
Gating=Special Clock for C2C_CLK=
0 = Masks=
1 = Passes=
0x1=
CLK_=
SFRCDREXP2=x0]=RW=
Gating=all Clocks for AXI2APB_CDREXP2=
0 = Masks=
1 = Passes=
0x1=
=
5.9.1.49 C2C_MONITOR 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4910, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0x0=
FSM_SEC=
_CURR_STATb=x3:0]=o=Current ptate of C2C internal FSM (for debugging 
only)=0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-81  
5.9.1.50 CLKOUT_CMU_CORE 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = MPLL_FOUT_RGT=
00101 ==ACLK_CORED=
00110== ACLK_COREP=
00111 ==SCLK_PWI=
01000== ACLK_R1Bu=
01001 = C2C_CLh=
0x0=
=
5.9.1.51 CLKOUT_CMU_CORE_DIV_STAT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x4A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIs_CLKOUT Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
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Exynos 5250_UM 5 Clock Controller 
 5-82  
5.9.1.52 C2C_CONFIG 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x6000, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
CG [31] RW Clock Gating 0x1 
MO [30] RW Master On 0x0 
FCLK_FREQ [29:20] RW Function Clock Frequency 0x32 
TXW [19:18] RW Tx Width 0x2 
RXW [17:16] RW Rx Width 0x2 
RSTn [15] RW Reset 0x1 
MD [14] RW Memory Done 0x0 
RET_RSTn [13] RW Retention Reset 0x1 
BASE_ADDRESS [12:3] RW Base Address 0x180 
SIZE [2:0] RW Size 0x4
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Exynos 5250_UM 5 Clock Controller 
 5-83  
5.9.1.53 CLK_DIV_ACP 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0x0=
PCLK_ACP_RATIl=[6:4]=RW=
DIV_ACP_PCLK=Clock divider Ratio=
PCLK_ACP=
= ACLK_ACP/(PCLK_ACP_RATIO + 1)=
0x0=
RSVD=[3]=–=Reserved=0x0=
ACLK_ACP_RATIl=[2:0]=RW=
DIV_ACP_ACLK=Clock divider Ratio=
ACLK_ACm=
= MPLLOUT/(ACLK_ACP_RATIO + 1)=
0x0=
=
5.9.1.54 CLK_DIV_STAT_ACP 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
DIV_PCLK_ACP=[4]=o=
DIV_ACP_PCLK=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_ACLK_ACP=[0]=o=
DIV_ACP_ACLK=status=
0 = Stable=
1 = Divider is changing=
0x0=
=
=
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Exynos 5250_UM 5 Clock Controller 
 5-84  
5.9.1.55 CLK_GATE_IP_ACP 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8800, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0xFF_FFFc=
CLK_SMMUG2a=x7]=RW=
Gating all=Clocks for=SMMUG2a=
0 = Mask=
1 = Passes=
0x1=
CLK_SMMUSSp=xS]=RW=
Gating all clocks for SMMUSSp=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUMDMA=x5]=RW=
Gating all=Clocks for=SMMUMDMA=
0 = Masks=
1 = Passes=
0x1=
CLK_ID=
_REMAPPEo=x4]=RW=
Gating all=Clocks for=ID_REMAPPEo=
0 = Masks=
1 = Passes=
0x1=
CLK_G2a=x3]=RW=
Gating all=Clocks for=G2a=
0 = Masks=
1 = Passes=
0x1=
CLK_SSp=x2]=RW=
Gating all=Clocks for=SSp=
0 = Masks=
1 = Passes=
0x1=
CLK_MDMA=x1]=RW=
Gating all=Clocks for=MDMA=
0 = Masks=
1 = Passes=
0x1=
CLK_SECJTAd=x0]=RW=
Gating all=Clocks for=SECJTAd=
0 = Masks=
1 = Passes=
0x1=
=
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