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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-267  
4.4.1.389 GPV2CONPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0070, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV2[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Output 0 
0x1 = Output 1 
0x2 = Input 
0x3 = Previous state 
0x00 
 
4.4.1.390 GPV2PUDPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0074, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV2[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x00
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Exynos 5250_UM 4 Pad Control 
 4-268  
4.4.1.391 GPV3CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0080, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GPV3CON[7] [31:28] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[15] 
0x3 to 0xE = Reserved 
0xF = EXT_INT63[7] 
0x00 
GPV3CON[6] [27:24] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[14] 
0x3 to 0xE = Reserved 
0xF = EXT_INT63[6] 
0x00 
GPV3CON[5] [23:20] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[13] 
0x3 to 0xE = Reserved 
0xF = EXT_INT63[5] 
0x00 
GPV3CON[4] [19:16] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[12] 
0x3 to 0xE = Reserved 
0xF = EXT_INT63[4] 
0x00 
GPV3CON[3] [15:12] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[11] 
0x3 to 0xE = Reserved 
0xF = EXT_INT63[3] 
0x00 
GPV3CON[2] [11:8] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[10] 
0x3 to 0xE = Reserved 
0xF = EXT_INT63[2] 
0x00 
GPV3CON[1] [7:4] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[9] 
0x3 to 0xE = Reserved 
0xF = EXT_INT63[1] 
0x00 
GPV3CON[0] [3:0] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_TXD[8] 
0x3 to 0xE = Reserved 
0xF = EXT_INT63[0] 
0x00
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Exynos 5250_UM 4 Pad Control 
 4-269  
4.4.1.392 GPV3DAT 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0084, Reset Value = 0x00 
Name Bit Type Description Reset Value 
GPV3DAT[7:0] [7:0] RWX 
When you configure the port as input port, the 
corresponding bit is the pin state. When you configure 
the port as output port, the pin state is the same as the 
corresponding bit. W hen you configure the port as 
functional pin, the undefined value will be read. 
0x00 
 
4.4.1.393 GPV3PUD 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0088, Reset Value = 0x5555 
Name Bit Type Description Reset Value 
GPV3PUD[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x5555 
 
4.4.1.394 GPV3DRV 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x008C, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
GPV3DRV[n] 
[2n + 1:2n] 
n = 0 to 7 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 7 RW Reserved. Should be zero. 0x00_0000
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Exynos 5250_UM 4 Pad Control 
 4-270  
4.4.1.395 GPV3CONPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0090, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV3[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Output 0 
0x1 = Output 1 
0x2 = Input 
0x3 = Previous state 
0x00 
 
4.4.1.396 GPV3PUDPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0094, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV3[n] [2n + 1:2n] 
n = 0 to 7 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x00
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Exynos 5250_UM 4 Pad Control 
 4-271  
4.4.1.397 ETC8PUD 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x00A8, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
ETC8PUD[n] [2n + 1:2n] 
n = 0 to 1 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x0000 
 
ETC8PUD[1:0] controls Xc2cTXCLK[0]. 
ETC8PUD[3:2] controls Xc2cTXCLK[1]. 
 
4.4.1.398 ETC8DRV 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x00AC, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
ETC8DRV[n] 
[2n + 1:2n] 
n = 0 to 1 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 1 RW Reserved. Should be zero. 0x00_0000 
 
ETC8DRV[1:0] controls Xc2cTXCLK[0]. 
ETC8DRV[3:2] controls Xc2cTXCLK[1].
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Exynos 5250_UM 4 Pad Control 
 4-272  
4.4.1.399 GPV4CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x00C0, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GPV4CON[1] [7:4] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_W KREQOUT 
0x3 to 0xE = Reserved 
0xF = EXT_INT64[1] 
0x00 
GPV4CON[0] [3:0] RW 
0x0 = Input 
0x1 = Output 
0x2 = C2C_W KREQIN 
0x3 to 0xE = Reserved 
0xF = EXT_INT64[0] 
0x00 
 
4.4.1.400 GPV4DAT 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x00C4, Reset Value = 0x00 
Name Bit Type Description Reset Value 
GPV4DAT[1:0] [1:0] RWX 
When you configure the port as input port, the 
corresponding bit is the pin state. When you configure 
the port as output port, the pin state is the same as the 
corresponding bit. W hen you configure the port as 
functional pin, the undefined value will be read. 
0x00 
 
4.4.1.401 GPV4PUD 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x00C8, Reset Value = 0x0005 
Name Bit Type Description Reset Value 
GPV4PUD[n] [2n + 1:2n] 
n = 0 to 1 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x0005
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Exynos 5250_UM 4 Pad Control 
 4-273  
4.4.1.402 GPV4DRV 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x00CC, Reset Value = 0x00_0000 
Name Bit Type Description Reset Value 
GPV4DRV[n] 
[2n + 1:2n] 
n = 0 to 1 RW 
0x0 = 1x 
0x2 = 2x 
0x1 = 3x 
0x3 = 4x 
0x00_0000 
[n + 16:16] 
n = 0 to 1 RW Reserved. Should be zero. 0x00_0000 
 
4.4.1.403 GPV4CONPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x00D0, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV4[n] [2n + 1:2n] 
n = 0 to 1 RW 
0x0 = Output 0 
0x1 = Output 1 
0x2 = Input 
0x3 = Previous state 
0x00 
 
4.4.1.404 GPV4PUDPDN 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x00D4, Reset Value = 0x0000 
Name Bit Type Description Reset Value 
GPV4[n] [2n + 1:2n] 
n = 0 to 1 RW 
0x0 = Disables Pull-up/down  
0x1 = Enables Pull-down  
0x2 = Reserved 
0x3 = Enables Pull-up  
0x00
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Exynos 5250_UM 4 Pad Control 
 4-274  
4.4.1.405 EXT_INT60CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0700, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
EXT_INT60=
_CON[7]=[30:28]=RW=
Setting the signaling method=of EXT_INT60[7]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT60=
_CON[6]=[26:24]=RW=
Setting the signaling method=of EXT_INT60[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[23]=–=Reserved=0x0=
EXT_INT60=
_CON[5]=[22:20]=RW=
Setting the signaling method=of EXT_INT60[5]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[19]=–=Reserved=0x0=
EXT_INT60=
_CON[4]=[18:16]=RW=
Setting the signaling method=of EXT_INT60[4]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[15]=–=Reserved=0x0=
EXT_INT60=
_CON[3]=[14:12]=RW=
Setting the signaling method=of EXT_INT60[3]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[11]=–=Reserved=0x0=
EXT_INT60=[10:8]=RW=Setting the signaling method=of EXT_INT60[2]=0x0=
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Exynos 5250_UM 4 Pad Control 
 4-275  
Name Bit Type Description Reset Value 
_CON[2] 0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge triggered 
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
RSVD [7] – Reserved 0x0 
EXT_INT60 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT60[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT60 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT60[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0
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Exynos 5250_UM 4 Pad Control 
 4-276  
4.4.1.406 EXT_INT61CON 
 Base Address: 0x10D1_0000 
 Address = Base Address + 0x0704, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
EXT_INT61=
_CON[7]=[30:28]=RW=
Setting the signaling method=of EXT_INT61[7]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT61=
_CON[6]=[26:24]=RW=
Setting the signaling method=of EXT_INT61[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[23]=–=Reserved=0x0=
EXT_INT61=
_CON[5]=[22:20]=RW=
Setting the signaling method=of EXT_INT61[5]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[19]=–=Reserved=0x0=
EXT_INT61=
_CON[4]=[18:16]=RW=
Setting the signaling method=of EXT_INT61[4]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[15]=–=Reserved=0x0=
EXT_INT61=
_CON[3]=[14:12]=RW=
Setting the signaling method=of EXT_INT61[3]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=
RSVD=[11]=–=Reserved=0x0=
EXT_INT61=[10:8]=RW=Setting the signaling method=of EXT_INT61[2]=0x0=
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