Samsung Exynos 5 User Manual
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Samsung Confidential Exynos 5250_UM 4 Pad Control 4-17 Register Offset Description Reset Value EXT_INT60_PEND 0x0A00 External interrupt EXT_INT60 Pending register 0x0000_0000 EXT_INT61_PEND 0x0A04 External interrupt EXT_INT61 Pending register 0x0000_0000 EXT_INT62_PEND 0x0A08 External interrupt EXT_INT62 Pending register 0x0000_0000 EXT_INT63_PEND 0x0A0C External interrupt EXT_INT63 Pending register 0x0000_0000 EXT_INT64_PEND 0x0A10 External interrupt EXT_INT64 Pending register 0x0000_0000 EXT_INT_GRPPRI _XC 0x0B00 External interrupt group priority control register 0x0000_0000 EXT_INT_PRIORITY _XC 0x0B04 External interrupt priority control register 0x0000_0000 EXT_INT_SERVICE _XC 0x0B08 Current service register 0x0000_0000 EXT_INT_SERVICE _PEND_XC 0x0B0C Current service pending register 0x0000_0000 EXT_INT_GRPFIXPRI_X C 0x0B10 External interrupt group fixed priority control register 0x0000_0000 EXT_INT60_FIXPRI 0x0B14 External interrupt 1 fixed priority control register 0x0000_0000 EXT_INT61_FIXPRI 0x0B18 External interrupt 2 fixed priority control register 0x0000_0000 EXT_INT62_FIXPRI 0x0B1C External interrupt 3 fixed priority control register 0x0000_0000 EXT_INT63_FIXPRI 0x0B20 External interrupt 4 fixed priority control register 0x0000_0000 EXT_INT64_FIXPRI 0x0B24 External interrupt 5 fixed priority control register 0x0000_0000 Base Address: 0x0386_0000 Register Offset Description Reset Value GPZCON 0x0000 Port group GPZ configuration register 0x0000_0000 GPZDAT 0x0004 Port group GPZ data register 0x00 GPZPUD 0x0008 Port group GPZ pull-up/down register 0x1555 GPZDRV 0x000C Port group GPZ drive strength 0x00_0000 GPZCONPDN 0x0010 Port group GPZ power down mode configuration register 0x0000 GPZPUDPDN 0x0014 Port group GPZ power down mode pull-up/down register 0x0000 EXT_INT50_CON 0x0700 External interrupt EXT_INT50 configuration register 0x0000_0000 EXT_INT50_FLTCON0 0x0800 External interrupt EXT_INT50 filter configuration register 0 0x0000_0000 EXT_INT50_FLTCON1 0x0804 External interrupt EXT_INT50 filter configuration register 1 0x0000_0000 EXT_INT50_MASK 0x0900 External interrupt EXT_INT50 mask register 0x0000_007F EXT_INT50_PEND 0x0A00 External interrupt EXT_INT50 pending register 0x0000_0000 EXT_INT_GRPPRI_XD 0x0B00 External interrupt group priority control register 0x0000_0000 EXT_INT_PRIORITY _XD 0x0B04 External interrupt priority control register 0x0000_0000 EXT_INT_SERVICE 0x0B08 Current service register 0x0000_0000
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-18 Register Offset Description Reset Value _XD EXT_INT_SERVICE _PEND_XD 0x0B0C Current service pending register 0x0000_0000 EXT_INT_GRPFIXPRI _XD 0x0B10 External interrupt group fixed priority control register 0x0000_0000 EXT_INT50_FIXPRI 0x0B14 External interrupt 1 fixed priority control register 0x0000_0000
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-19 4.4.1.1 GPA0CON Base Address: 0x1140_0000 Address = Base Address + 0x0000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value GPA0CON[7] [31:28] RW 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = I2C_2_SCL 0x4 = HS-I2C_2_SCL 0x5 to 0xE = Reserved 0xF = EXT_INT1[7] 0x00 GPA0CON[6] [27:24] RW 0x0 = Input 0x1 = Output 0x2 = Reserved 0x3 = I2C_2_SDA 0x4 = HS-I2C_2_SDA 0x5 to 0xE = Reserved 0xF = EXT_INT1[6] 0x00 GPA0CON[5] [23:20] RW 0x0 = Input 0x1 = Output 0x2 to 0xE = Reserved 0xF = EXT_INT1[5] 0x00 GPA0CON[4] [19:16] RW 0x0 = Input 0x1 = Output 0x2 to 0xE = Reserved 0xF = EXT_INT1[4] 0x00 GPA0CON[3] [15:12] RW 0x0 = Input 0x1 = Output 0x2 = UART_0_RTSn 0x3 to 0xE = Reserved 0xF = EXT_INT1[3] 0x00 GPA0CON[2] [11:8] RW 0x0 = Input 0x1 = Output 0x2 = UART_0_CTSn 0x3 to 0xE = Reserved 0xF = EXT_INT1[2] 0x00 GPA0CON[1] [7:4] RW 0x0 = Input 0x1 = Output 0x2 = UART_0_TXD 0x3 to 0xE = Reserved 0xF = EXT_INT1[1] 0x00 GPA0CON[0] [3:0] RW 0x0 = Input 0x1 = Output 0x2 = UART_0_RXD 0x3 to 0xE = Reserved 0xF = EXT_INT1[0] 0x00
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-20 4.4.1.2 GPA0DAT Base Address: 0x1140_0000 Address = Base Address + 0x0004, Reset Value = 0x00 Name Bit Type Description Reset Value GPA0DAT[7:0] [7:0] RWX When you configure the port as input port, the corresponding bit is the pin state. When you configure the port as output port, the pin state is similar as the corresponding bit. W hen you configure the port as functional pin, you can read the undefined value. 0x00 4.4.1.3 GPA0PUD Base Address: 0x1140_0000 Address = Base Address + 0x0008, Reset Value = 0x5555 Name Bit Type Description Reset Value GPA0PUD[n] [2n + 1:2n] n = 0 to 7 RW 0x0 = Disables Pull-up/down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up 0x5555 4.4.1.4 GPA0DRV Base Address: 0x1140_0000 Address = Base Address + 0x000C, Reset Value = 0x00_0000 Name Bit Type Description Reset Value GPA0DRV[n] [2n + 1:2n] n = 0 to 7 RW 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x 0x00_0000 [n + 16:16] n = 0 to 7 RW Reserved. Should be zero. 0x00_0000
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-21 4.4.1.5 GPA0CONPDN Base Address: 0x1140_0000 Address = Base Address + 0x0010, Reset Value = 0x0000 Name Bit Type Description Reset Value GPA0[n] [2n + 1:2n] n = 0 to 7 RW 0x0 = Output 0 0x1 = Output 1 0x2 = Input 0x3 = Previous state 0x00 4.4.1.6 GPA0PUDPDN Base Address: 0x1140_0000 Address = Base Address + 0x0014, Reset Value = 0x0000 Name Bit Type Description Reset Value GPA0[n] [2n + 1:2n] n = 0 to 7 RW 0x0 = Disables Pull-up/down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up 0x00
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-22 4.4.1.7 GPA1CON Base Address: 0x1140_0000 Address = Base Address + 0x0020, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value GPA1CON[5] [23:20] RW 0x0 = Input 0x1 = Output 0x2 = UART_3_TXD 0x3= Reserved 0x4 = UART_AUDIO_TXD 0x5 to 0xE = Reserved 0xF = EXT_INT2[5] 0x00 GPA1CON[4] [19:16] RW 0x0 = Input 0x1 = Output 0x2 = UART_3_RXD 0x3= Reserved 0x4 = UART_AUDIO_RXD 0x5 to 0xE = Reserved 0xF = EXT_INT2[4] 0x00 GPA1CON[3] [15:12] RW 0x0 = Input 0x1 = Output 0x2 = UART_2_RTSn 0x3 = I2C_3_SCL 0x4 = HS-I2C_3_SCL 0x5 to 0xE = Reserved 0xF = EXT_INT2[3] 0x00 GPA1CON[2] [11:8] RW 0x0 = Input 0x1 = Output 0x2 = UART_2_CTSn 0x3 = I2C_3_SDA 0x4 = HS-I2C_3_SDA 0x5 to 0xE = Reserved 0xF = EXT_INT2[2] 0x00 GPA1CON[1] [7:4] RW 0x0 = Input 0x1 = Output 0x2 = UART_2_TXD 0x3= Reserved 0x4 = UART_AUDIO_TXD 0x5 to 0xE = Reserved 0xF = EXT_INT2[1] 0x00 GPA1CON[0] [3:0] RW 0x0 = Input 0x1 = Output 0x2 = UART_2_RXD 0x3= Reserved 0x4 = UART_AUDIO_RXD 0x5 to 0xE = Reserved 0xF = EXT_INT2[0] 0x00
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-23 4.4.1.8 GPA1DAT Base Address: 0x1140_0000 Address = Base Address + 0x0024, Reset Value = 0x00 Name Bit Type Description Reset Value GPA1DAT[5:0] [5:0] RWX When you configure the port as input port, the corresponding bit is the pin state. When you configure the port as output port, the pin state is similar as the corresponding bit. W hen you configure the port as functional pin, the undefined value will be read. 0x00 4.4.1.9 GPA1PUD Base Address: 0x1140_0000 Address = Base Address + 0x0028, Reset Value = 0x0555 Name Bit Type Description Reset Value GPA1PUD[n] [2n + 1:2n] n = 0 to 5 RW 0x0 = Disables Pull-up/down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up 0x0555 4.4.1.10 GPA1DRV Base Address: 0x1140_0000 Address = Base Address + 0x002C, Reset Value = 0x00_0000 Name Bit Type Description Reset Value GPA1DRV[n] [2n + 1:2n] n = 0 to 5 RW 0x0 = 1x 0x2 = 2x 0x1 = 3x 0x3 = 4x 0x00_0000 [n + 16:16] n = 0 to 5 RW Reserved. Should be zero. 0x00_0000
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-24 4.4.1.11 GPA1CONPDN Base Address: 0x1140_0000 Address = Base Address + 0x0030, Reset Value = 0x0000 Name Bit Type Description Reset Value GPA1[n] [2n + 1:2n] n = 0 to 5 RW 0x0 = Output 0 0x1 = Output 1 0x2 = Input 0x3 = Previous state 0x00 4.4.1.12 GPA1PUDPDN Base Address: 0x1140_0000 Address = Base Address + 0x0034, Reset Value = 0x0000 Name Bit Type Description Reset Value GPA1[n] [2n + 1:2n] n = 0 to 5 RW 0x0 = Disables Pull-up/down 0x1 = Enables Pull-down 0x2 = Reserved 0x3 = Enables Pull-up 0x00
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-25 4.4.1.13 GPA2CON Base Address: 0x1140_0000 Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value GPA2CON[7] [31:28] RW 0x0 = Input 0x1 = Output 0x2 = SPI_1_MOSI 0x3 to 0xE = Reserved 0xF = EXT_INT3[7] 0x00 GPA2CON[6] [27:24] RW 0x0 = Input 0x1 = Output 0x2 = SPI_1_MISO 0x3 to 0xE = Reserved 0xF = EXT_INT3[6] 0x00 GPA2CON[5] [23:20] RW 0x0 = Input 0x1 = Output 0x2 = SPI_1_nSS 0x3 = Reserved 0x4 = Reserved 0x5 to 0xE = Reserved 0xF = EXT_INT3[5] 0x00 GPA2CON[4] [19:16] RW 0x0 = Input 0x1 = Output 0x2 = SPI_1_CLK 0x3 = Reserved 0x4 = Reserved 0x5 to 0xE = Reserved 0xF = EXT_INT3[4] 0x00 GPA2CON[3] [15:12] RW 0x0 = Input 0x1 = Output 0x2 = SPI_0_MOSI 0x3 = I2C_5_SCL 0x4 to 0xE = Reserved 0xF = EXT_INT3[3] 0x00 GPA2CON[2] [11:8] RW 0x0 = Input 0x1 = Output 0x2 = SPI_0_MISO 0x3 = I2C_5_SDA 0x4 to 0xE = Reserved 0xF = EXT_INT3[2] 0x00 GPA2CON[1] [7:4] RW 0x0 = Input 0x1 = Output 0x2 = SPI_0_nSS 0x3 = I2C_4_SCL 0x4 to 0xE = Reserved 0xF = EXT_INT3[1] 0x00 GPA2CON[0] [3:0] RW 0x0 = Input 0x1 = Output 0x00
Samsung Confidential Exynos 5250_UM 4 Pad Control 4-26 Name Bit Type Description Reset Value 0x2 = SPI_0_CLK 0x3 = I2C_4_SDA 0x4 to 0xE = Reserved 0xF = EXT_INT3[0]