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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-18  
Name Bit Type Description Reset Value 
010 = 96 bytes 
011 = 128 bytes 
100 = 160 bytes 
101 = 192 bytes 
110 = 224 bytes 
111 = 256 bytes 
[Channel 1] 
000 = 8 byte 
001 = 16 bytes 
010 = 24 bytes 
011 = 32 bytes 
100 = 40 bytes  
101 = 48 bytes 
110 = 56 bytes  
111 = 64 bytes 
[Channel 2, 3] 
000 = 2 byte  
001 = 4 bytes 
010 = 6 bytes  
011 = 8 bytes 
100 = 10 bytes 
101 = 12 bytes 
110 = 14 bytes 
111 = 16 bytes 
RSVD [3] – Reserved 0 
Tx FIFO 
Reset [2] RW 
Auto-clears after resetting FIFO 
0 = Normal 
1 = Tx FIFO reset 
0 
Rx FIFO 
Reset [1] RW 
Auto-clears after resetting FIFO 
0 = Normal 
1 = Rx FIFO reset 
0 
FIFO Enable [0] RW 0 = Disables 
1 = Enables 0 
NOTE: When the UART does not reach the FIFO trigger level and does not receive data during the specified timeout interval 
in DMA receive mode with FIFO, the Rx interrupt will be generated (receive time out). You must check the FIFO 
status and read out the rest.
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-19  
12.6.1.4 UMCONn (n = 0, 1, 2, 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x000C, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0=
RTS trigger 
level=[7:5]=RW=
Determines=the trigger level of=Rx=FIFO=to control nRTS 
signal. When AFC bit is enabled=and Rx FIFO have bytes=
that are greater than or equal to the trigger level,=nRTS=
signal is deactivated.=
[Channel 0]=
000 = 255 bytes=
001 = 224 bytes=
010 = 192 bytes=
011 = 160 bytes=
100 = 128 bytes=
101 = 96 bytes=
110 = 64 bytes=
111 = 32 bytes=
[Channel 1]=
000 = 63 bytes=
001 = 56 bytes=
010 = 48 bytes=
011 = 40 bytes=
100 = 32 bytes=
101 = 24 bytes=
110 = 16 bytes=
111 = 8 bytes=
[Channel 2]=
000 = 15 bytes=
001 = 14 bytes=
010 = 12 bytes=
011 = 10 bytes=
100 = 8 bytes=
101 = 6 bytes=
110 = 4 bytes=
111 = 2 bytes=
000=
Auto flow 
control (AFC)=[4]=RW=0 = Disables=
1 = Enables=0=
Modem 
interrupt enable=x3]=RW=0== Disables=
1 = Enables=0=
oSVa=x2:1]=RW=These bits must be=0=00=
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-20  
Name Bit Type Description Reset Value 
Request to 
send [0] RW 
When AFC bit is enabled, this value is ignored. In this case 
the Exynos 5250 controls nRTS signals automatically. 
When AFC bit is disabled, the software must control nRTS 
signal. 
0 = H level (Inactivate nRTS)            
1 = L level (Activate nRTS) 
0 
NOTE:  
1. UART 2 supports AFC function, when XuRTSn_2 and XuCTSn_2 are set as nRTS2 and nCTS2 by GPA1CON.   
  UART 3 does not support AFC function, because the Exynos 5250 does not contain nRTS3 and nCTS3. 
2. In AFC mode, Rx FIFO trigger level should be set to lower than RTS trigger level, because transmitter stops data 
  transfer when it gets deactivated nRST signal.
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-21  
12.6.1.5 UTRSTATn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0010, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:24] –=Reserved=0=
ox=FIFO=
count in Rx=
time-out 
status=
[23:16]=o=ox=FIFO counter capture value when ox=time-out occurs=0x00=
Tx=DMA 
FSM state=[15:12]=o=
Current State of Tx=DMA FSM 
0x0 = IDLE 
0x1 = Burst Request 
0x2 = Burst Acknowledgement 
0x3 = Burst Next (intermediate state for next request) 
0x4 = Single Request 
0x5 = Single Acknowledgement 
0x6 = Single Next (intermediate state for next request) 
0x7 = Last Burst Request 
0x8 = Last Burst Acknowledgement 
0x9 = Last Single Request 
0x10 = Last Single Acknowledgement 
0x0 
Rx DMA 
FSM state [11:8] R 
Current State of Rx DMA FSM 
0x0 = IDLE 
0x1 = Burst Request 
0x2 = Burst Acknowledgement 
0x3 = Burst Next (intermediate state for next request) 
0x4 = Single Request 
0x5 = Single Acknowledgement 
0x6 = Single Next (intermediate state for next request) 
0x7 = Last Burst Request 
0x8 = Last Burst Acknowledgement 
0x9 = Last Single Request 
0x10 = Last Single Acknowledgement 
0x0 
RSVD [7:4] –=Reserved=0=
ox=time-out 
status/clear1 [3] R/W 
Rx Time-out status when read 
0 = Rx Time out did not occur 
1 = Rx Time out 
Clear Rx Time-out status when write 
0 = No operation 
1 = Clears Rx Time-out status 
NOTE: If UCONn[10] is set to 1, writing 1 to this bit resumes 
Rx DMA FSM that was suspended when Rx time-out had 
0
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-22  
Name Bit Type Description Reset Value 
occurred. 
Transmitter 
empty [2] R 
This bit is automatically set to 1 when the transmit buffer 
has no valid data to transmit, and the transmit shift is empty. 
0 = Buffer is not empty 
1 = Transmitter (that includes transmit buffer and shifter) 
empty 
1 
Transmit 
buffer empty [1] R 
This bit is automatically set to 1 when transmit buffer is 
empty. 
0 = Buffer is not empty  
1 = Buffer is empty  
In Non-FIFO mode, Interrupt or DMA is requested.  
In FIFO mode, Interrupt or DMA is requested, when Tx  
FIFO Trigger Level is set to 00 (empty) 
When UART uses FIFO, check Tx FIFO Count bits and Tx 
FIFO Full bit in UFSTAT instead of this bit. 
1 
Receive 
buffer data 
ready 
[0] R 
This bit is automatically set to 1 if receive buffer contains 
valid data, received through the RXDn port. 
0 = Buffer is empty  
1 = Buffer has a received data  
(In Non-FIFO mode, Interrupt or DMA is requested) 
When UART uses the FIFO, check Rx FIFO Count bits and 
Rx FIFO Full bit in UFSTAT instead of this bit.  
0
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-23  
12.6.1.6 UERSTATn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0014, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0=
Break 
detect=[3]=o=
This bit is automatically set to=1 to indicate that a break signal 
has been received.=
0 = No break=signal is=received=
1 = Break signal is=received=(Interrupt is requested)==
0=
Frame 
error=[2]=o=
This bit is automatically set to=1 when a Frame Error occurs 
during=the receive operation.=
0 = No=Frame Error occurs=during=the receive=operation=
1 = Frame Error occurs=(interrupt is requested)=during=the receive=
operation=
0=
Parity error=[1]=o=
This bit is automatically set to=1 when a Parity Error occurs=
during=the=receive operation.=
0 = No=Parity Error=occurs=during receive=operation=
1 = Parity Error=occurs=(interrupt is requested)=during=the receive=
operation=
0=
Overrun 
error=[0]=o=
This bit is automatically set to=1 automatically when an Overrun 
Error occurs during the receive operation.=
0 = No=Overrun Error occurs=during=the receive=operation=
1 = Overrun Error=occurs=(interrupt is requested)=during the=
receive=operation=
0=
NOTE: These bits (UERSATn[3:0]) are automatically cleared to 0 when UART error status is read.
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-24  
12.6.1.7 UFSTATn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0018, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0=
Tx FIFO full=x24]=o=
This bit is automatically set to=1 when=the transmitted=FIFO=
is full during transmit operation.=
0 = Not cull=
1 = Full=
0=
Tx FIFO 
count=x23:16]=o=Number of data in Tx FIFl=
NOTE: This field is set to=0=when=Tx FIFO is full.=0=
oSVa=x15:10]=–=Reserved=0=
Rx FIFO 
error=[9]=o=
This bit is set to=1=when=Rx FIFO contains invalid data 
which results due to=crame=brror, marity brror, or=Break=
pignal.=
0=
Rx FIFO full=x8]=o=
This bit is automatically set to=1 when=the received=FIFO is 
full during receive operation.=
0 = Not cull=
1 = Full=
0=
Rx FIFO 
count=x7:0]=o=Number of data in Rx FIFl=
NOTE: This field is set to=0=when=Rx FIFO is full.=0=
=
=
=
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-25  
12.6.1.8 UMSTATn (n = 0, 1, 2, 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x001C, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0=
Delta CTp=x4]=o=
This bit indicates=that the nCTp=input to the=Exynos 5250=
has changed its state since the last time it was read by CPU.=
(Refer to Figure 12-9 for more information.) 
0 = Not changed 
1 = Changed 
0 
RSVD [3:1] –=Reserved=-=
Clear to send=[0]=o=
0== CTS signal is not activated (nCTS pin is high)=
1 = CTS signal is activated (nCTS pin is low)=
NOTE: In UMSTATn of UART4 and ISm-UART, reset value 
of this bit is undefined. It depends on the GPIO configuration=
of the corresponding CTS port.=
0=
=
Figure 12-9 illustrates the nCTS and Delta CTS Timing diagram. 
 
    Figure 12-9   nCTS and Delta CTS Timing Diagram 
 nCTS
Delta CTS
Read_UMSTAT
Modem_interrupt
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-26  
12.6.1.9 UTXHn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0020, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=–=
UTXHn=[7:0]=t=Transmit=Data for UARTn=–=
=
12.6.1.10 URXHn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0024, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0=
URXHn=[7:0]=o=Receive Data for UARTn=0x00=
NOTE: When an Overrun Error occurs, the URXHn must be read. If not, the next received data makes an Overrun Error, 
even though the overrun bit of UERSTATn had been cleared. 
 
12.6.1.11 UBRDIVn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0028, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0=
UBRDIVn=[15:0]=RW=Baud=Rate Division Value=
NOTE: UBRDIV value must be=greater than 0.=0x0000=
=
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Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-27  
12.6.1.12 UFRACVALn (n = 0 to 4)  
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x002C, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0=
rFRACVALn=x3:0]=RW=Determines=the fractional part of=Baud oate aivisor=0x0=
=
1. UART Baud Rate Configuration 
 The value stored in the Baud Rate Divisor (UBRDIVn) and Divisor Fractional value (UFRACVALn) is  
  used to determine the serial Tx/Rx clock rate (baud rate) as: 
 DIV_VAL = UBRDIVn + UFRACVALn/16 
 Or 
 DIV_VAL = (SCLK_UART/(bps  16)) – 1 
 Where, the divisor should be from 1 to (216 – 1). 
 Using UFRACVALn, you can generate the Baud Rate more accurately. 
 
 For example, when the Baud Rate is 115200 bps and SCLK_UART is 40 MHz, UBRDIVn and UFRACVALn are: 
 DIV_VAL = (40000000/(115200  16)) – 1 
  = 21.7 – 1  
  = 20.7 
 UBRDIVn = 20 (integer part of DIV_VAL) 
 UFRACVALn/16 = 0.7  
 so, UFRACVALn = 11 
 
2. Baud Rate Error Tolerance 
 UART Frame error should be less than 1.87 % (3/160) 
 tUPCLK = (UBRDIVn + 1 + UFRACVAL/16)  16  1Frame/SCLK_UART     
 tUPCLK: Real UART Clock 
  tEXTUARTCLK = 1Frame/baud-rate                                                           
   tEXTUARTCLK: Ideal UART Clock  
 UART error = (tUPCLK – tEXTUARTCLK)/tEXTUARTCLK  100 % 
 * 1Frame = start bit + data bit + parity bit + stop bit. 
 
3. UART Clock and PCLK Relation 
   
  There is a constraint on the ratio of clock frequencies for PCLK to UARTCLK. 
  
 The frequency of UARTCLK must not be more than 5.5/3 times faster than the frequency of PCLK: 
 
  FUARTCLK  5.5/3  FPCLK
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