Samsung Exynos 5 User Manual
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Samsung Confidential Exynos 5250_UM 15 Display Controller 15-39 15.3.8 VTIME Controller VTIME comprises of two blocks, namely: VTIME_RGB_TV for RGB timing control VTIME_I80 for indirect i80 interface timing control 15.3.8.1 RGB Interface Controller VTIME generates control signals for the RGB interface: RGB_VSYNC RGB_HSYNC RGB_VDEN RGB_VCLK These control signals configure the VIDTCON0/1/2 registers in the VSFR register. The VTIME module generates programmable control signals that support various display devices. These control signals are based on the programmable configuration of display control registers in the VSFR. The LCD line pointer moves to the first pixel of the top of display. The configuration of HOZVAL field and LINEVAL registers, control the pulse generation, of RGB_VSYNC and RGB_HSYNC, respectively. The size of the LCD panel considers this equation to determine HOZVAL and LINEVAL: HOZVAL = (Horizontal display size) – 1 LINEVAL = (Vertical display size) – 1 The CLKVAL field in VIDCON0 register controls the rate of RGB_VCLK signal. Table 15-5 describes the relationship between RGB_VCLK and CLKVAL. The minimum value of CLKVAL is 1. RGB_VCLK (Hz) = H CLK/(CLKVAL + 1), where CLKVAL >= 1
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Table 15-6 describes the relation 16-bpp between VCLK and CLKVAL.
Table 15-6 Relation 16-bpp between VCLK and CLKVAL (TFT, Frequency of Video Clock Source = 300
MHz)
CLKVAL 300 MHz/X VCLK
2 300 MHz/3 100.0 MHz
3 300 MHz/4 75.0 MHz
: : :
63 300 MHz/64 4.6875 MHz
VSYNC, VBPD, VFPD, HSYNC, HBPD, HFPD, HOZVAL, and LINEVAL configure RGB_HSYNC and
RGB_VSYNC signal.
The frame rate is the frequency of RGB_VSYNC. The frame rate is associated with the value of VSYNC, VBPD,
VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL registers. Most LCD drivers require their own
adequate frame rate.
Use this equation to calculate the frame rate:
Frame Rate = 1/[{(VSPW + 1) + (VBPD + 1) + (LIINEVAL + 1) + (VFPD + 1) } {(HSPW + 1) + (HBPD + 1)
+ (HFPD + 1) + (HOZVAL + 1) } {(CLKVAL + 1)/(Frequency of Clock source)}]
Samsung Confidential Exynos 5250_UM 15 Display Controller 15-41 15.3.8.2 I80 Interface Controller VTIME_I80 controls display controller for CPU style LDI. It has the following functions: Generates I80 Interface Control Signals CPU style LDI Command Control Timing Control for VDMA and VDPRCS 15.3.8.3 Output Control Signal Generation VTIME_I80 generates SYS_CS0, SYS_CS1, SYS_WE, and SYS_RS control signals (For Timing Diagram, refer to Figure 15-19). Their timing parameters, LCD_CS_SETUP, LCD_WR_SETUP, LCD_WR_ACT, and LCD_WR_HOLD are set through I80IFCONA0 and I80IFCONA1 SFRs. 15.3.8.4 Partial Display Control Although partial display is the main feature of CPU style LDI, VTIME_I80 does not support this function in hardware logic. This function is implemented by SFR setting (LINEVAL, HOZVAL, OSD_LeftTopX_F, OSD_LeftTopY_F, OSD_RightBotX_F, OSD_RightBotY_F, PAGEWIDTH, and OFFSIZE). 15.3.8.5 LDI Command Control LDI receives both command and data. Command specifies an index for selecting the SFR in LDI. In control signal for command and data, only SYS_RS signal has a special function. Usually, SYS_RS has a polarity of 1 for issuing command and vice versa. Display controller has one command control: Normal command
Samsung Confidential Exynos 5250_UM 15 Display Controller 15-42 15.3.9 Setting of Commands 15.3.9.1 Normal Command To execute Normal command, follow these steps: Put commands into LDI_CMD0 to 11 (maximum 12 commands). Set CMDx_EN in LDI_CMDCON0 to enable normal command (For example, if you want to enable command 4, you have to set CMD4_EN to 0x01). Set NORMAL_CMD_ST in I80IFCONB0/1. The display controller has the following characteristics for command operations: Normal command mode is possible for each of the 12 commands. Sends 12 maximum commands between frames in its normal operation (Normal operation means ENVID = 1 and video data is displayed in LCD panel). Issues commands in the order of CMD0 CMD1 CMD2 CMD3 … CMD10 CMD11. Skips disabled commands (CMDx_EN = 0x0). Sends over 12 commands (Possible in Normal command and system initialization). Set 12 LDI_CMDx, CMDx_EN, and CMDx_RS. Set NORMAL_CMD_ST. Read NORMAL_CMD_ST with polling. If 0, go to NORMAL_CMD_ST setting.
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15.3.9.1.1 Indirect I80 Interface Trigger
VTIME_I80 starts its operation when a software trigger occurs. There are two kinds of triggers. However, software
trigger is generated by setting TRGCON SFR.
15.3.9.2 Interrupt
Completion of one frame generates Frame Done Interrupt.
15.3.9.2.1 Indirect I80 Interface Output Mode
The following table shows the output mode of Indirect i80 interface based on mode @ VIDCON0.
Table 15-7 i80 Output Mode
VIDCON0
Register Value BPP Bus
Width Split DATA Command
I80_EN 1 24 24 X {R[7:0], G[7:0], B[7:0]} CMD[23:0]
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15.3.10 Virtual Display
The display controller supports horizontal or vertical scrolling of the hardware. When the screen scrolls, you
should change values of LCDBASEU and LCDBASEL (refer to Figure 15-16 for more information). However, do
not change the values of PAGEWIDTH and OFFSIZE. The size of video buffer that stores the image should be
larger than the screen of the LCD panel.
Figure 15-16 illustrates an example of scrolling in virtual display.
Figure 15-16 Scrolling in Virtual Display This is t he data of line 1 of v irt ual s c reen. This is t he data of line 1 of v irt ual s c reen.
This is t he data of line 2 of v irt ual s c reen. This is t he data of line 2 of v irt ual s c reen.
This is t he data of line 3 of v irt ual s c reen. This is t he data of line 3 of v irt ual s c reen.
This is t he data of line 4 of v irt ual s c reen. This is t he data of line 4 of v irt ual s c reen.
This is t he data of line 5 of v irt ual s c reen. This is t he data of line 5 of v irt ual s c reen.
This is t he data of line 6 of v irt ual s c reen. This is t he data of line 6 of v irt ual s c reen.
This is t he data of line 7 of v irt ual s c reen. This is t he data of line 7 of v irt ual s c reen.
This is t he data of line 8 of v irt ual s c reen. This is t he data of line 8 of v irt ual s c reen.
This is t he data of line 9 of v irt ual s c reen. This is t he data of line 9 of v irt ual s c reen.
This is t he data of line 10 of v irtual s c reen. This is t he data of line 10 of v irtual s c reen.
This is t he data of line 11 of v irtual s c reen. This is t he data of line 11 of v irtual s c reen.
.
..
Bef ore Sc rolling
View Port
(The s am e s ize
of LCD panel)
LIN EVAL + 1
OFFSI ZEPAGEW ID TH
This is t he data of line 1 of v irt ual s c reen. This is t he data of line 1 of v irt ual s c reen.
This is t he data of line 2 of v irt ual s c reen. This is t he data of line 2 of v irt ual s c reen.
This is t he data of line 3 of v irt ual s c reen. This is t he data of line 3 of v irt ual s c reen.
This is t he data of line 4 of v irt ual s c reen. This is t he data of line 4 of v irt ual s c reen.
This is t he data of line 5 of v irt ual s c reen. This is t he data of line 5 of v irt ual s c reen.
This is t he data of line 6 of v irt ual s c reen. This is t he data of line 6 of v irt ual s c reen.
This is t he data of line 7 of v irt ual s c reen. This is t he data of line 7 of v irt ual s c reen.
This is t he data of line 8 of v irt ual s c reen. This is t he data of line 8 of v irt ual s c reen.
This is t he data of line 9 of v irt ual s c reen. This is t he data of line 9 of v irt ual s c reen.
This is t he data of line 10 of v irtual s c reen. This is t he data of line 10 of v irtual s c reen.
This is t he data of line 11 of v irtual s c reen. This is t he data of line 11 of v irtual s c reen.
.
..
Af ter Sc rolling
LCDBASEU
LCDBASEL
OFFSI ZE
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15.3.11 RGB Interface Specification
15.3.11.1 Signals
Table 15-8 describes the RGB I/F signal.
Table 15-8 RGB I/F Signal Description
Signal Input/Output Description
LCD_HSYNC Output (Internal I/F) Horizontal Sync. Signal
LCD_VSYNC Output (Internal I/F) Vertical Sync. Signal
LCD_VCLK Output (Internal I/F) LCD Video Clock
LCD_VDEN Output (Internal I/F) Data Enable
LCD_VD[23:0] Output (Internal I/F) YCbCr Data Output
15.3.11.2 RGB Interface Timing
Figure 15-17 illustrates the RGB interface timings.
Figure 15-17 RGB Interface Timing VSYNC
HSYNC
VDEN
VSPW+1VBPD+1VFPD+1LINEVAL+1
1 FRAME
VDEN
HSPW+1HBPD+1HFPD+1HOZVAL+1
HSYNC
VCLK
VD
1 LINE
INT_FrSyn
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15.3.11.3 Parallel Output (Internal I/F)
This section describes general 24-bit output
15.3.11.3.1 General 24-bit Output
Figure 15-18 illustrates the RGB interface timing (RGB parallel).
Figure 15-18 RGB Interface Timing (RGB Parallel)
InValid DataInvalid Data
RGB_HSYNC
RGB_VCLK
RGB_DATA [23:16]
RGB_VDEN
HACTHFHBHS
1 Line
Display
N
M
R0
G0B0
Image data
N
M
Image SourceOutput
Parallel
(general)
R0
G0B0
InValid DataInvalid Data
InValid DataInvalid Data
[15: 8]
[ 7: 0]
R0
G0
B0BN-1
RN-1
GN-1
R1
G1
B1
R2
G2
B2
RN-2
GN-2
BN-2
= N
Samsung Confidential Exynos 5250_UM 15 Display Controller 15-47 15.3.12 LCD Indirect i80 System Interface 15.3.12.1 Signals Signal Input/Output Description SYS_VD[17:0] Input/Output (Internal I/F) Video Data SYS_CS0 Output (Internal I/F) Chip select for LCD0 SYS_CS1 Output (Internal I/F) Chip select for LCD1 SYS_WE Output (Internal I/F) Write enable SYS_OE Output (Internal I/F) Output enable SYS_RS/SYS_ADD[0] Output (Internal I/F) Address Output SYS_ADD[0] is Register/ State select NOTE: MIPI DSI mode (when VIDCON0 [30] = 1) SYS_ADD[1] = SYS_ST: 0 when VDOUT is from Frame SYS_ADD[1] = SYS_ST: 1 when VDOUT is from Command
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15.3.12.2 Indirect i80 System Interface WRITE Cycle Timing
Figure 15-19 Indirect i80 System Interface WRITE Cycle Timing
LCD_CS_SETUP+1
LCD_WR_SETUP+1
LCD_WR_ACT+1
LCD_WR_HOLD+1
VCLK(internal)
SYS_RS
SYS_CSn
SYS_WE
SYS_VD
LCD_CS_SETUP=0,LCD_WR_SETUP=0,LCD_WR_ACT=0,LCD_WR_HOLD=0