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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-227  
Name Bit Type Description Reset Value 
_CON[2] 0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
RSVD [7] – Reserved 0x0 
EXT_INT22 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT22[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT22 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT22[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0
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Exynos 5250_UM 4 Pad Control 
 4-228  
4.4.1.321 EXT_INT14_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0800, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN1[3] [31] RW 
Enables Filter for EXT_INT14[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[3] [30:24] RW Filtering width of EXT_INT14[3] 0x00 
FLTEN1[2] [23] RW 
Enables Filter for EXT_INT14[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[2] [22:16] RW Filtering width of EXT_INT14[2] 0x00 
FLTEN1[1] [15] RW 
Enables Filter for EXT_INT14[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[1] [14:8] RW Filtering width of EXT_INT14[1] 0x00 
FLTEN1[0] [7] RW 
Enables Filter for EXT_INT14[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[0] [6:0] RW Filtering width of EXT_INT14[0] 0x00
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    							Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-229  
4.4.1.322 EXT_INT14_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0804, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN1[7] [31] RW 
Enables Filter for EXT_INT14[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[7] [30:24] RW Filtering width of EXT_INT14[7] 0x00 
FLTEN1[6] [23] RW 
Enables Filter for EXT_INT14[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[6] [22:16] RW Filtering width of EXT_INT14[6] 0x00 
FLTEN1[5] [15] RW 
Enables Filter for EXT_INT14[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[5] [14:8] RW Filtering width of EXT_INT14[5] 0x00 
FLTEN1[4] [7] RW 
Enables Filter for EXT_INT14[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[4] [6:0] RW Filtering width of EXT_INT14[4] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-230  
4.4.1.323 EXT_INT15_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0808, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0000=
FLTEN2[1]=[15]=RW=
Enables Filter=for EXT_INT15[1]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH2[1]=[14:8]=RW=Filtering width of EXT_INT15[1]=0x00=
FLTEN2[0]=[7]=RW=
Enables Filter=for EXT_INT15[0]=
0x0 = Disables=
0x1 = Enables=
0x0=
FLTWIDTH2[0]=[6:0]=RW=Filtering width of EXT_INT15[0]=0x00=
=
4.4.1.324 EXT_INT15_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x080C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-231  
4.4.1.325 EXT_INT16_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0810, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN3[3] [31] RW 
Enables Filter for EXT_INT16[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[3] [30:24] RW Filtering width of EXT_INT16[3] 0x00 
FLTEN3[2] [23] RW 
Enables Filter for EXT_INT16[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[2] [22:16] RW Filtering width of EXT_INT16[2] 0x00 
FLTEN3[1] [15] RW 
Enables Filter for EXT_INT16[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[1] [14:8] RW Filtering width of EXT_INT16[1] 0x00 
FLTEN3[0] [7] RW 
Enables Filter for EXT_INT16[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH3[0] [6:0] RW Filtering width of EXT_INT16[0] 0x00 
 
4.4.1.326 EXT_INT16_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0814, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-232  
4.4.1.327 EXT_INT17_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0818, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN4[3] [31] RW 
Enables Filter for EXT_INT17[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[3] [30:24] RW Filtering width of EXT_INT17[3] 0x00 
FLTEN4[2] [23] RW 
Enables Filter for EXT_INT17[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[2] [22:16] RW Filtering width of EXT_INT17[2] 0x00 
FLTEN4[1] [15] RW 
Enables Filter for EXT_INT17[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[1] [14:8] RW Filtering width of EXT_INT17[1] 0x00 
FLTEN4[0] [7] RW 
Enables Filter for EXT_INT17[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH4[0] [6:0] RW Filtering width of EXT_INT17[0] 0x00 
 
4.4.1.328 EXT_INT17_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x081C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0x00000000=
=
=
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Exynos 5250_UM 4 Pad Control 
 4-233  
4.4.1.329 EXT_INT18_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0820, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN5[3] [31] RW 
Enables Filter for EXT_INT18[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[3] [30:24] RW Filtering width of EXT_INT18[3] 0x00 
FLTEN5[2] [23] RW 
Enables Filter for EXT_INT18[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[2] [22:16] RW Filtering width of EXT_INT18[2] 0x00 
FLTEN5[1] [15] RW 
Enables Filter for EXT_INT18[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[1] [14:8] RW Filtering width of EXT_INT18[1] 0x00 
FLTEN5[0] [7] RW 
Enables Filter for EXT_INT18[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[0] [6:0] RW Filtering width of EXT_INT18[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-234  
4.4.1.330 EXT_INT18_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0824, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN5[7] [31] RW 
Enables Filter for EXT_INT18[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[7] [30:24] RW Filtering width of EXT_INT18[7] 0x00 
FLTEN5[6] [23] RW 
Enables Filter for EXT_INT18[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[6] [22:16] RW Filtering width of EXT_INT18[6] 0x00 
FLTEN5[5] [15] RW 
Enables Filter for EXT_INT18[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[5] [14:8] RW Filtering width of EXT_INT18[5] 0x00 
FLTEN5[4] [7] RW 
Enables Filter for EXT_INT18[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH5[4] [6:0] RW Filtering width of EXT_INT18[4] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-235  
4.4.1.331 EXT_INT19_FLTCON0 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x0828, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN6[3] [31] RW 
Enables Filter for EXT_INT19[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[3] [30:24] RW Filtering width of EXT_INT19[3] 0x00 
FLTEN6[2] [23] RW 
Enables Filter for EXT_INT19[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[2] [22:16] RW Filtering width of EXT_INT19[2] 0x00 
FLTEN6[1] [15] RW 
Enables Filter for EXT_INT19[1] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[1] [14:8] RW Filtering width of EXT_INT19[1] 0x00 
FLTEN6[0] [7] RW 
Enables Filter for EXT_INT19[0] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[0] [6:0] RW Filtering width of EXT_INT19[0] 0x00
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Exynos 5250_UM 4 Pad Control 
 4-236  
4.4.1.332 EXT_INT19_FLTCON1 
 Base Address: 0x1340_0000 
 Address = Base Address + 0x082C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN6[7] [31] RW 
Enables Filter for EXT_INT19[7] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[7] [30:24] RW Filtering width of EXT_INT19[7] 0x00 
FLTEN6[6] [23] RW 
Enables Filter for EXT_INT19[6] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[6] [22:16] RW Filtering width of EXT_INT19[6] 0x00 
FLTEN6[5] [15] RW 
Enables Filter for EXT_INT19[5] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[5] [14:8] RW Filtering width of EXT_INT19[5] 0x00 
FLTEN6[4] [7] RW 
Enables Filter for EXT_INT19[4] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH6[4] [6:0] RW Filtering width of EXT_INT19[4] 0x00
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