GE Logiq P5 Service Manual
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GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL Section 5-4 - Main Board Detail 5 - 9 Section 5-4 Main Board Detail The Front End generates the strong burst transmitted by the probes as ultrasound into the body. It also receives weak ultrasound echoes from blood cells and body structure, amplifies these signals and converts them to an digital signal. Figure 5-8 LOGIQ™ P5 Main board Structure Figure 5-9 LOGIQ™ A5/A5Pro Main board Structure P3RLY ASSY CL1TRX ASSY ACWD ASSY (option) SYSCONPM ASSY BACKPLANE ASSY ASIG ASSY ARP ASSY TX and RX SignalsDigital Data and Power USB, Audio I/O, Video I/O etc. APS ASSY 4D BOX ASSY (Option) Front End Back End P3RLY ASSY CL1TRX ASSY P3RLY ASSY CL1TRX ASSY ACWD ASSY (option) SYSCONPM ASSY BACKPLANE ASSY ASIG ASSY ARP ASSY TX and RX SignalsDigital Data and Power USB, Audio I/O, Video I/O etc. APS ASSY 4D BOX ASSY (Option) Front End Back End P3RLY ASSY CL1TRX ASSY P3RLY ASSY CL1TRX ASSY ACWD ASSY (option) SYSCONPM ASSY BACKPLANE ASSY ASIG ASSY ARP ASSY TX and RX SignalsDigital Data and Power USB, Audio I/O, Video I/O etc. APS ASSY 4D BOX ASSY (Option) Front End Back End P3RLY ASSY CL1TRX ASSY P3RLY ASSY CL1TRX ASSY ACWD ASSY (option) SYSCONPM ASSY BACKPLANE ASSY ASIG ASSY ARP ASSY TX and RX SignalsDigital Data and Power USB, Audio I/O, Video I/O etc. APS ASSY 4D BOX ASSY (Option) Front End Back End ACWD ASSY (option) SYSCONPM ASSY BACKPLANE ASSY ASIG ASSY ARP ASSY TX and RX SignalsDigital Data and Power USB, Audio I/O, Video I/O etc. APS ASSY 4D BOX ASSY (Option) Front End Back End
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL 5 - 10Section 5-4 - Main Board Detail Section 5-4 Main Board Detail (cont’d) The digital representation of this signal is presented to the Mid Processor section. • P3RLY (Relay) : This P3RLY is for LOGIQ™ P5 or LOGIQ™ A5/A5Pro with 3port upgrade kit. P3RLY Assy contains 3 connectors for probe in terface and arrays of relays for switchable connection. High voltage multiplexer provide connection between 128 signal of probe and selectable 64 channels transmit/receive signals. • P2RLY(Relay) : This P2RLY is for LOGIQ™ A5/A 5Pro. P2RLY Assy contains 2 connectors for probe interface and arrays of relays for switchable connection. High voltage multiplexer provide connection between 128 signal of probe and sele ctable 64 channels transmit/receive signals • CL1TRX (Color single acquisition Tx and Rx) : This board is for LOGIQ™ P5 and LOGIQ™ A5/ A5Pro with Color upgrade. This co nsists of two main board, L1BFC(Single acquisition Beam Forming Control) and CTX(Color TX) ASSY. L1BFC has transmit/receiving s witch to isolate rx signal circuit from transmit pulse. The preamplifier on L1BFC amplifies 64 small echo signals. The amplified receiving signals are converted to digital and sent to the delayed summing block. CTX board has 64 channel Transmit pulse generator, bipolar pulse drivers and delay controller. • SYSCONPM (System Control board with Pentium M module): SYSCONPM is for LOGIQ™ P5 or LOGIQ™ A5/A5Pro with color upgrade kit. SYSC ONPM controls scan operation and transfer the scan parameters to other boards like P3RLY, CL1TRX, ACWD(option). Proper signal processing for tissue and Doppler are done in SYSCONPM. • SYSCONCM (System Control boar d with Celeron M module): SYSCONCM is for LOGIQ™ A5/ A5Pro. SYSCONPM controls scan operation and tr ansfer the scan parameters to other boards like P2RLY, BL1TRX. Proper signal processing for tissue and Doppler are done in SYSCONCM. • APS/APS Pro(Advanced Power Supply ) : Includes Low voltage power and High voltage power in one module. It generates 3.3V, 5V, and 12V for digital parts and 6V, -6V, 12A, -12V for analog parts. Additionally, It generate THV(Transmit High Voltage) and SHV(Static High Voltage) for transmit pulse driver and High voltage MUX. • ASIG(Signal) : Transfers the TX pulse signals from CL1TRX(BL1TRX) to the probe port on P3RLY(P2RLY). Receives echo signals from P3 RLY(P2RLY) are transfer to CL1TRX(BL1TRX) through this ASIG. For ACWD, the pre-amplified received signals go to the ACWD though ASIG.
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL Section 5-4 - Main Board Detail 5 - 11 5-4-1 P3RLY and P2RLY P3RLY ASSY contains of 3 probe connectors and provides switchable connection between probes and 64ch transmitters/receivers. P2 RLY contains 2 probe connector The main function of P3RLY ASSY and P2RLY ASSY is as follows. - 3-to-1 selectors with three probe ports for P3RLY board. - 2 to 1 selector with two probe ports for P2RLY board - Interface with FEBUS (control bus) - Supply/Cut control and failure detection of supply voltage for Mu x circuit in a Probe. - Device: Mechanical Relay. 5-4-1-1 Interface to Probe • Probe Status detection- Detects whether or not a probe is connected.(POPEN) - Detects ID code of a connected probe.(PCODE) • Mux Interface - Transfers control data of Mux to a probe.(CONSYS,CONSTA) - Enables/Disables control of data. - Detects whether Mux data setting is finished or not. • Power Supply for Mux - Supply/Cut control:+5V and +12V on a connector are supplied while a probe is connected to the connector. +/-SHV are supplied only while a probe is selected. • LED Blinking - The LED in a probe blinks when the probe is selected. Figure 5-10 P3RLY & P2RLY Block Diagram PORT A PORT B RELAY HV MUX Control CircuitControl FPGA Probe ID Interface 128 128 128To CL1TRX SHV FEBUS 64 PORT A PORT B RELAY HV MUX Control CircuitControl FPGA Probe ID Interface 128 128 128To CL1TRX SHV FEBUS 64 PORT A PORT B PORT C RELAY RELAY HV MUX Cont r ol Ci r cui tCont r ol FPGATemperat ure Sensor Probe I D I nt erf ace 128 128 128 128 128To CL1TRX SHV FEBUS 64 PORT A PORT B PORT C RELAY RELAY HV MUX Cont r ol Ci r cui tCont r ol FPGATemperat ure Sensor Probe I D I nt erf ace 128 128 128 128 128To CL1TRX SHV FEBUS 64
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL 5 - 12Section 5-4 - Main Board Detail 5-4-2 CL1TRX and BL1TRX 5-4-2-1 Overview CL1TRX have two PWAs. Both are CTX PWA and L1BFC PWA. CTX generates the TX pulse and L1BFC receives the echo signal to amplify it and co nvert the amplified echo signal into digital signal. These RF digital signals delayed and summed by beam-forming in OQx2 ASICs. BL1TRX have also two PWAs, BTX PWA and L1BFC PWA. The difference between BTX and CTX is trasntmit pulse firver circuit. BTX have single pu lse driver per each channel, but the CTX have dual pulse driver circuit per each channel for high performance in B/CFM mode The CL1TRX ASSY or BL1TRX ASSY is located in the Nest box 5-4-2-2 Limiter in CL1TRX and BL1TRX The main functions are as follows. • 64ch transmit/receiving switches protect a Pre-amp from a high voltage transmit pulse Figure 5-11 LMT Block Diagram From TX _ Bl o c k +V bias -V bias To RX _ Bl o c k To P 3 RL Y board CouplingDiode Isolation Diode3 3 3 3 3
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL Section 5-4 - Main Board Detail 5 - 13 5-4-2-3 Preamp in CL1TRX/BL1TRX The Pre-Amplifier rece ives and amplifies each 64 echo signals. Then, all 64 echo signals (from 0 to 63ch) are outputted to the Analog to Digital converter to delay and sum. Following 32 echo signals (from 32 to 63ch) are simultaneously outputted to the ACWD ASSY via the ASIG ASSY. The preamp module have main three blocks: Pre-amp and Gain Control and Mode control block. The preamp module amplifies the echo signals. The mode control block selects a maximum gain code via dedicated control signals from SYSCONPM(SYSC ONCM). The analog signal provided by Gain Control block gives total amplified gain. The block di agram above of the preamp module for a received signal is given. Actually, there are 64 channels equivalent to figure above for a preamp module. The Pre-amp block consists of Low Noise Amplif ier (LNA) and Variable Gain Amplifier (VGA). A received signal is amplified by LNA (fixed gain), then amplified by VGA (variable gain). Figure 5-12 Pre Amp Block Diagram For a Channel LN Ach0 VCA LN Ach 1 VCA LN Ach2 VCA LN Ach3 VCA LN Ach63 VCA A D C 10bits A D C 10bits A D C 10bits A D C 10bits A D C 10bits LN Ach0 VCA LN Ach 1 VCA LN Ach2 VCA LN Ach3 VCA LN Ach63 VCA A D C 10bits A D C 10bits A D C 10bits A D C 10bits A D C 10bits
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL 5 - 14Section 5-4 - Main Board Detail 5-4-2-4 Delayed Sum Module The Delayed Sum is the receive beam former and consist of 4 OQx2 ASICs. Each OQx2 ASIC has 16 receiving channels. The each digital beamforming output data of the OQx2 transferred to the next OQx2 and the output of final OQx2 transferred to the SYSCONP M(SYSCONCM)to make it into image data through some digital signal processing. Delay control data for receive beam forming are contained in SDRAM. Typically only 1 selected probe data are saved in SDRAM. If new probe is connected, additional probe data will be downloaded from HDD to SDRAM. Main items are • TRBC FPGA : Provide interf aces with SYSCONPM(SYSCONCM)thr ough FE Bus. This FPGA control all OQx2 asic for receive beamforming. A ll of parameter information for ASIC operation are loaded into OQX2 ASIC from SYSC ONPM(SYSCONCM) through this FPGA. • OQX2 :Digital receive beamforming ASIC. Each OQ X2 have capability of 16 channel receiving data inputs. Each input data can be 12 bits. Operation clock is 40 MHz. 4 OQX2 ASICs are used in a Delayed Sum module and each OQX2 summed output are cascaded to next OQX2 ASIC. So, the last summed output of the last OQX2 are tr ansferred to SYSCONPM(SYSCONCM) to make a meaningful image data. The receive beamforming control logic in OQX2 ASIC need delay information data for each channels control logic. This delay information data are downloaded into ASIC from SDRAM by TRBC FPGA. • SDRAM(TD and RD Memory) : SDRAM keeps the rece ive delay data for OQX2 ASIC. During scan time, these data are downloaded into OQX2 ASIC by TRBC FPGA. Memory capacity is 32Mbytes for a probe. Figure 5-13 DELAYED SUM Block Diagram A D C 10bits A D C 10bits A D C 10bits A D C 10bits A D C 10bits OQX2 OQX2 OQX2 OQX2 SDRAM fo r OQx2 & TPG2 Cl1TRX RF_SUM F E B U S BACKPLANE ASSY A D C 10bits A D C 10bits A D C 10bits A D C 10bits A D C 10bits OQX2 OQX2 OQX2 OQX2 SDRAM fo r OQx2 & TPG2 Cl1TRX RF_SUM F E B U S BACKPLANE ASSY
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL Section 5-4 - Main Board Detail 5 - 15 5-4-2-5 Transmit Pulse Generation Block The CTX in CL1TRX generate bipolar transmit pulse and have dual driver for each scan mode, for example, low voltage driver for PWD or CFM and high voltage for B. This board has 64 channels transmit signal drivers, Transmit Pulse Generator ASIC, control FPGA and so on. Transmit pulse are generated by TPG2 ASIC. Each TPG2 ASIC makes 16 channels signals, so total 4 ASIC are used in CTX in CL1TRX. All of control inform ations for pulse generation, pulse width, time delay of each channel are come from SYSCONPM( SYSCONCM) in real time via Backplane. The control FPGA, TRBC FPGA provide interface between SYSC ONPM(SYSCONCM) and TPG2 ASICs and control operation condition of CTX in CL 1TRX Main items are • TPG2 ASIC: A TPG2 ASIC can generate 16 channels logic level transmit pulse signal. This ASIC use 2 phase 40MHz clocks for transmit delay cont rol and pulse generation. 40Mhz operation clocks are come from L1SYSCON assy via Backplane. • Transmit Pulse Driver : TPG2 ASIC generated logic level signal for transmit pulse. So this signal need to be expanded to high voltage signal. Driver circuit make logic level signal to high voltage level signal. • THV Switch : LOGIQ™ P5 system use dual transmi t high voltage for transmit driver because B mode and CFM mode use different voltage level of transmit pulse. So in duplex of triplex mode, B/ CFM or B/DOP, Low THV and High THV are swit ched in CTX in CL1TRX in real time. • TRBC FPGA : This FPGA is located on L1 BFC board interfacing with SYSCONPM(SYSCONCM) and updating the TPG data in real time. Figure 5-14 Tx pulse Generation Block Diagram TPG2 TX Driver_HVL (C T X O n ly) TX Driver_HVH Selection BufferTPG2 TPG2 TPG2 64ch TX signal fo r H V L 64ch TX signal fo r H V H TPG2 Control Signal Probe Interface Board Buffer enable signal to s e le c t T X D rive r TPG2 TX Driver_HVL (C T X O n ly) TX Driver_HVH Selection BufferTPG2 TPG2 TPG2 64ch TX signal fo r H V L 64ch TX signal fo r H V H TPG2 Control Signal Probe Interface Board Buffer enable signal to s e le c t T X D rive r
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL 5 - 16Section 5-4 - Main Board Detail 5-4-3 SYSCONPM(SYSCONCM) 5-4-3-1 Overview SYSCONPM(SYSCONCM) ASSY includes Mi d processor and Back End Processor. DSP generate the scan control data and the FEBC FPGA adjust the ti me and manipulate the FEBUS to control Front End boards and APS/APS Pro. CPDI tran sfer the Image or Doppler data to the Image Ring buffer through DSP. Finally the data goes to the SOM module to make displaying image or sound. 5-4-3-2 SYSTEM ON MODULE(SOM) The SYSCONPM(SYSCONCM) Assy has S ystem On Module PC(SOM) and PWA which is able to dock SOM. In LOGIQ™ P5 system and LOGIQ™ P5 system, PWA is used the same one. But the System On Module, which computes received Scan data, and interfaces the external peripheral devices (ex. B/ W printer, Digital Video Recorder etc.) are divided high grade for LOGIQ™ P5 and low grade for LOGIQ™ A5/A5Pro by its CPU performance. Figure 5-15 SYSCONPM( SYSCONCM) Block Diagram
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL Section 5-4 - Main Board Detail 5 - 17 5-4-3-3 PERIPHERAL BLOCK • IDE Interface : SYSCONPM(SYSCONCM) Assy has SATA bus for HDD and PATA bus for DVD-R drive interface. - Primary Master SATA: HDD - Secondary Master PATA: DVD-R Drive • DISPLAY (VGA, DVI, TV input) BLOCK Basically SOM support 2 kinds of display output. One is LVDS level for Plat panel display, and other is analog RGB for CRT monitor. To obtain advanced and stable quality image, S YSCONPM(SYSCONCM) Assy convert LVDS signal to Digital Video Interface (DVI) and transport TMDS signal to main display of system. • ETHERNET BLOCK SOM on the SYSCONPM(SYSCONCM) has one integrat ed Ethernet port : Intel 82562 10/100 Mbps Fast Ethernet controller • SOM supply four USB 1.1/2.0 port. Each USB port s are used for the keyboard, BW digital printer, USB port for usb memory stick, etc. • VCR INPUT For Video play back, SYSCONPM(SYSCONCM) has Video Decoder device. It support NTSC/ PAL mode both. It transfers encoded data to SOM through PCI bus. - Supports capture resolutions up to 768x576(Full PAL mode) - CCIR 656 Interface - S-Video & composite input interface 5-4-3-4 FPGA BLOCK • FEBC FPGA(FEBUS Control): A major function of FEBC is that generate FEBUS to control scan sequence, access register on the each other front end assy, and interface to DSP through EMIFB bus. Other roles are below - Generates a stable PGC curve for getting better image quality. - Gathers the diagnostic information: LV, HV, Probe temperature, Nest temperature. - Supervises the system safety - Manages the each ASSY info rmation with IIC Bus: SYSCONPM(SYSCONCM), CL1TRX, P3RLY(P2RL), ACWD (option) and Probes - Controls HV Voltage output level: Transfer the voltage refe rence data from DSP to APS/APS Pro via IIC interface. • CPDI FPGA(CHACOM Processing Data Interface): The major function of CPDI is that transfer mid processed data from CHACOM to DSP local process. CPDI has 2EA 8x1024 Dual port as one scan line image data buffer. Address sequencer indicates to DSP that buffered data is full one scan line. then DSP can transfer a scan line data to ones SDRAM. For debugging, CPDI generate test pattern image data. It will be able to check CHACOM run normally. 5-4-3-5 CLOCK DISTRIBUTION BLOCK Each operation clock is divided from 160MHz. Also ECL logic is used to remove clock skew for all clock distribution. Required clocks is following: • 40MHz In-phase and 40MHz Quad-phase for ACWD, CL1TRX assy • 40MHz In-phase for P3RLY assy
GE HEALTHCARE DIRECTION 5394141, REVISION 1LOGIQ™ P5 SERVICE MANUAL 5 - 18Section 5-4 - Main Board Detail 5-4-3-6 POWER CONTROL BLOCK ON/OFF power sequence control is needed to prevent system to boot up abnormally, and protect to loose important diagnostic information of patient from unexpected power failure. • Live power : Whenever main AC powe r is supplied, Microprocessor on the SYSCON PM(SYSCONCM) must live always by live power supp lied by APS/APS Pro Assy. • System boot-up sequence Peripheral power -> LV power -> SO M (Main PC) on the SYSCONPM(SYSCONCM). • Software shut down sequence Because not ATX power, Main Operation System (Windows XP) have to inform about time to shutdown to DSP by interrupt. So D SP can allow FPGA to assert shutdown signal to MICOM. • Abnormal shut down sequence SYSCONPM(SYSCONCM) can force to shutdown system abnormally by pressing power button during 15 second. But live power for MICOM has to alive. 5-4-3-7 CHACOM BLOCK This ASIC have two main function. One is the CHAF , which have functions of coded excitation decorder and 2nd harmonic filter. The othe r is COMSO, which has functions of detector, B/M mode edge enhance, Log compression, and dynamic range control. 5-4-3-8 PGC and TEST SIGNAL GENERATION BLOCK SYSCONPM(SYSCONCM) generate Power Gain Control signal in order to get better quality scan image from CL1TRX. This signal goes into a preamp on the CL1TRX(BL1TRX) Assy. Additionally, SYSCONPM(SYSCONCM) gener ate test signal used to test analog path of CL1TRX(BL1TRX) Assy. These signals are converted to analog from 8bit digital data from FEBC FPGA, and DSP could update digital PGC and Test data table whenever needed.