NEC Neax 2400 Ipx System Operations And Maintenance Manual

							NDA-24307 CHAPTER 2
Page 33
Issue 1
SYSTEM MAINTENANCE OUTLINE
Figure 2-23  General Block Diagram of the Whole System (2/2)
TSWM0TSWM1
TSWM0TSWM1
MISCIOCEMA
HSW
PLO
MISCIOCEMA
MISCIOCEMA
PLO
GT
ISAGT-B
TSW00TSW01TSW02TSW03
TSW00TSW01TSW02TSW03
TSW00TSW01TSW02TSW03
TSW00TSW01TSW02TSW03
IOGT
ISAGT
CPU
LANI
GT
ISAGT-A
CPULANI
Fusion Link
ISWLN2LN3
To TSW
of LN0To TSW
of LN1
To PLO of
  LN0/1
DLKC
GT
ISAGT-A
GT
ISAGT-B
CPULANI
TSW00TSW01TSW02TSW03
DLKCPLOCLK
To MUX
(IMG0)To MUX
(IMG1)
To MUX
(IMG0)To MUX
(IMG1)To MUX
(IMG2)To MUX
(IMG3)
To MUX
(IMG2)To MUX
(IMG3)
CLK
Note 2
Note 1
Note 3
Note 4
Note 4
Circuit Card 
(No. 0 System) 
Circuit Card 
(No. 1 System)
Note 1
HSW00, 01 for No. 0 System / 
HSW10, 11 for No. 1 System
Note 2
ISW-LN TSW CA-n Cables
Note 3
ISW-LN PLO CA-n Cables
Note 4
PLO-CLK CA-n Cables
:
:
< ISW (Inter-node Switch) >
ISAGT:  PZ-GT13          LANI:  PZ-PC19                 IOGT:  PH-GT10          TSW:  PU-SW00
HSW:  PU-SW01           PLO:  PH-CK16/17-A         EMA:  PH-PC40           IOC:  PH-IO24
< LN (Local Node) >
ISAGT-A:  PZ-GT13       ISAGT-B:  PZ-GT20           LANI:  PZ-PC19           GT:  PH-GT09              TSW:  PH-SW12          MUX:  PH-PC36 
DLKC:  PH-PC20           PLO:  PH-CK16-A             CLK:  PH-CK18            EMA:  PH-PC40           IOC:  PH-IO24
Note:For details on each equipment’s switching network, see Chapter 6, System Control Procedures. 
						

							CHAPTER 2 NDA-24307
Pag e 3 4
Issue 1
SYSTEM MAINTENANCE OUTLINE
Figure 2-24   CPU Controlling Block Diagram (ISW)
LPM of ISW
EMAIOC /
MISC
ISAGT 0
LANI
PWR
PWR
CPU 0
MEMORY
PCI BUSISA BUS
CPU board CPR
CPU clock
   CPR
(ST-BY)Reset Signal
(ST-BY)
MISC BUS
MISC BUS
T
M
IOGT 1IOGT 0IOP1IOP0
ISAGT 1CPU board
T
M
Fusion Link
PLO 0
PLO 1
MISC BUS MISC BUS
To TSWM1 of LN3
To TSWM0 of LN3
To TSWM1 of LN2
To TSWM0 of LN2
To TSWM1 of LN1
To TSWM0 of LN1
000 001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E  00F
TSW
TSW
TSW
TSW
TSW/
  INTTSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW TSW TSW TSW
TSW 00
010 011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
01E  01F
TSW
TSW
TSW
TSW
TSW/
  INTTSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW TSW TSW TSW
TSW 01
020 021
022
023
024
025
026
027
028
029
02A
02B
02C
02D
02E  02F
TSW
TSW
TSW
TSW
TSW/
  INTTSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW TSW TSW TSW
TSW 02
030 031
032
033
034 035
036
037
038
039
03A03B
03C
03D 03E  03F
TSW
TSW
TSW
TSW
TSW/
  INTTSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW TSW TSW TSW
TSW 03
110 111
112
113
114
115
116
117
118
119
11A
11B
11C
11D
11E
11F
TSW
TSW
TSW
TSW
TSW/
  INTTSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW TSW TSW TSW
TSW 11
120 121
122
123
124
125
126
127
128
129
12A
12B
12C
12D
12E
12F
TSW
TSW
TSW
TSW
TSW/
  INTTSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW TSW TSW TSW
TSW 12
130 131
132
133
134
135
136
137
138
139
13A
13B
13C
13D
13E
13F
TSW
TSW
TSW
TSW
TSW/
  INTTSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW TSW TSW TSW
TSW 13
HSW 00
HSW 11HSW 01
HSW 10
To TSWM1 of LN3
To TSWM0 of LN3
To TSWM1 of LN2
To TSWM0 of LN2
To TSWM1 of LN1
To TSWM0 of LN1
To TSWM1 of LN0
To TSWM0 of LN0
To TSWM1 of LN0
To TSWM0 of LN0
Note 2
This figure shows a block diagram of the CPU controlling block in ISW, where CPU 0 is active.
To LPM
of LN0To LPM
of LN1To LPM
of LN2To LPM
of LN3
- Symbols -
            :  Controlling Routes of CPU                :  Cable
            :  Circuit card (active)                    :  Circuit card (ST-BY)
            :  External Cable                            :  Clock Oscillator
            :  Signal
EMA:  PH-PC40
LANI:  PZ-PC19
IOC:  PH-IO24MUX:  PH-PC36
ISAGT:  PZ-GT13
IOGT:  PH-GT10TSW:  PH-SW00
PLO:  PH-CK16-A/17-A
CLK:  PH-CK18
TSW I/O BUS
ISWM
TSW I/O BUS
Note 2
Note 3
HSW:  PH-SW01
Note 1 Note 1
100 101
102
103
104
105
106
107
108
109
10A
10B
10C
10D
10E
10F
TSW
TSW
TSW
TSW
TSW/
  INTTSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW
TSW TSW TSW TSW
TSW 10
Note 1:The two HSW cards here provide the space division switching for a maximum of 16 PCM
highways from/to the TSW (PU-SW00) cards in ISWM. For more details, refer to NEAX2400 IPX
IPX-U “Circuit Card Manual”.
Note 2:See details in Figure 2-26, Speech Path Block Diagram.
Note 3:Multiple connection is provided on the backboard side between the PLOs here. For more details,
refer to the “Circuit Card Manual”.  
						

							NDA-24307 CHAPTER 2
Page 35
Issue 1
SYSTEM MAINTENANCE OUTLINE
Figure 2-25   CPU Controlling Block Diagram (LN)
EMAIOC /
MISCLANI
PWR
PWR
CPU 0
MEMORY
PCI BUSISA BUS
CPU board CPR
CPU clock
Reset Signal
(ST-BY)
MISC BUS
MISC BUS
TSWM 1 of LN0  
TSW 00TSW 01TSW 11TSW 10
CLK 0CLK 1
GT 1
GT 0IOP1
IOP0
TSW/INT TSW/INT TSW/INTTSW/INT
MUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXTSW
     02
TSW/
   INT
TSW 
     03
TSW/
   INT
TSW
     13
TSW/
   INT
TSW
     12
TSW/
   INT
TSW I/O
MISC BUS MISC BUS
BUS
TSW I/O BUS
ISAGT-0AT
MISAGT-0B
   CPR
(ST-BY)
ISAGT-A
TSWM 0 of LN0  
TSW 00TSW 01TSW 11TSW 10
PLO 0PLO 1
GT 1
GT 0IOP1
IOP0
TSW/INT TSW/INT TSW/INTTSW/INT
MUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXMUXTSW
     02
TSW/
   INT
TSW 
     03
To ISWM
TSW/
   INT
TSW
     13
TSW/
   INT
TSW
     12
TSW/
   INT
TSW I/O BUS
MISC BUS MISC BUS
MISC BUS
TSW I/O BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
IMG 0
PIM 3
PIM 2
PIM 1
PIM 0
ISAGT-B
LPM of LN0
Fusion Link
To LPM of ISW
This figure shows a block diagram of the CPU controlling block in LN0, where CPU 0 is active.
- Symbols -
          :  Controlling Routes of CPU                         :  Cable
            :  Circuit card (active)                  :  Circuit card (ST-BY)
            :  External Cable                         :  Clock Oscillator
            :  Signal
DLKC0/1
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
IMG 3
PIM 3
PIM 2
PIM 1
PIM 0
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
IMG 2
PIM 3
PIM 2
PIM 1
PIM 0
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
LC/TRK
MUX
MUXPM BUS
PM BUS
IMG 1
PIM 3
PIM 2
PIM 1
PIM 0
EMA:  PH-PC40
LANI:  PZ-PC19
IOC:  PH-IO24DLKC:  PH-PC20
MUX:  PH-PC36
ISAGT-A:  PZ-GT13
ISAGT-B:  PZ-GT20
GT:  PH-GT09TSW:  PH-SW12
PLO:  PH-CK16-A/17-A
CLK:  PH-CK18
Note 1
Note 2To ISWMNote 1To ISWMNote 1To ISWMNote 1
To LPM
of LN1To LPM
of LN2To LPM
of LN3
Note 1:See details in Figure 2-26, Speech Path Block Diagram.
Note 2:Multiple connection is provided on the backboard side between the PLOs here. For more
details, refer to the “Circuit Card Manual.” 
						

							CHAPTER 2 NDA-24307
Pag e 3 6
Issue 1
SYSTEM MAINTENANCE OUTLINE
Figure 2-26   Speech Path Block Diagram (1/2)
ISWM
MUXMUXLC/TRKPIM0
IMG0 of LN0
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG1 of LN0
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG2 of LN0
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG3 of LN0
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
- Symbols -
:  Cable:  Circuit card (ACT)
:  Circuit card (ST-BY)
:  Speech Path
TSW (in TSWM0/1) :  PH-SW12 TSW (in ISWM) :  PU-SW00
HSW:  PU-SW01
MUX:  PH-PC36
T
S
W
TSW/INT
TSW 00
T
S
W
00000100200300400500600700800900A00B00C00D00E00F
T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INT
TSW 10
T
S
W
10010110210310410510610710810910A10B10C10D10E10F
T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
W
HSW
T
S
W
TSW/INT
TSW 01
T
S
W
01001101201301401501601701801901A01B01C01D01E01F
T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INT
TSW 11
T
S
W
11011111211311411511611711811911A11B11C11D11E11F
T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
W
TSW/INTTSW/INT
TSW/INT
00800900A00B
00C00D00E00F
TSWM 0
  ( LN0)
M
U
X
TSW 00
M
U
XM
U
XM
U
X
TSW02
M
U
XM
U
XM
U
XM
U
XTSW/INT
M
U
XM
U
XM
U
XM
U
X
TSW 10
M
U
XM
U
XM
U
XM
U
X
TSW 12
M
U
X
TSW 01
M
U
XM
U
XM
U
X
TSW03
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 11
M
U
XM
U
XM
U
XM
U
X
TSW 13
TSW/INT
TSW/INTTSW/INT
TSW/INT000001002003 004005006007104105106107
100101102103
10810910A10B
10C10D10E10F
TSWM 1
  ( LN0)M
U
X
TSW 00
M
U
XM
U
XM
U
X
TSW02
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 10
M
U
XM
U
XM
U
XM
U
X
TSW 12
M
U
X
TSW 01
M
U
XM
U
XM
U
X
TSW03
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 11
M
U
XM
U
XM
U
XM
U
X
TSW 13
TSW/INT
TSW/INTTSW/INT
TSW/INT
TSW/INT
TSW/INTTSW/INT
TSW/INT000001002003 004005006007104105106107
100101102103
00800900A
00B 00C00D00E00F
10810910A10B
10C10D10E10F
MUXMUXLC/TRKPIM0
IMG0 of LN1
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG1 of LN1
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG2 of LN1
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG3 of LN1
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
TSWM 0
  ( LN1)
M
U
X
TSW 00
M
U
XM
U
XM
U
X
TSW02
M
U
XM
U
XM
U
XM
U
XTSW/INT
M
U
XM
U
XM
U
XM
U
X
TSW 10
M
U
XM
U
XM
U
XM
U
X
TSW 12
M
U
X
TSW 01
M
U
XM
U
XM
U
X
TSW03
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 11
M
U
XM
U
XM
U
XM
U
X
TSW 13TSW/INTTSW/INT
TSW/INT TSW/INT
TSW/INTTSW/INT
TSW/INT
000 001002003 004005006007
00800900A00B
00C00D00E00F104105106107
100101102103
10810910A10B
10C10D10E10F
TSWM 1
  ( LN1)
M
U
X
TSW 00
M
U
XM
U
XM
U
X
TSW02
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 10
M
U
XM
U
XM
U
XM
U
X
TSW 12
M
U
X
TSW 01
M
U
XM
U
XM
U
X
TSW03
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 11
M
U
XM
U
XM
U
XM
U
X
TSW 13
TSW/INT
TSW/INTTSW/INT
TSW/INT
TSW/INT
TSW/INTTSW/INT
TSW/INT000001002003 004005006007104105106107
100101102103
00800900A00B
00C00D00E00F 10810910A10B
10C10D10E10F
HSW
T
S
W
TSW/INTTSW 02
T
S
W02002102202302402502602702802902A02B02C02D02E02FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INTTSW 12
T
S
W12012112212312412512612712812912A12B12C12D12E12FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INTTSW 03
T
S
W03003103203303403503603703803903A03B03C03D03E03FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INTTSW 13
T
S
W13013113213313413513613713813913A13B13C13D13E13FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
W
To TSWM0
    of LN2To TSWM1
    of LN2To TSWM0
    of LN3To TSWM1
    of LN3To TSWM0
    of LN2To TSWM1
    of LN2To TSWM0
    of LN3To TSWM1
    of LN3
This figure shows a block diagram of speech path. 
						

							NDA-24307 CHAPTER 2
Page 37
Issue 1
SYSTEM MAINTENANCE OUTLINE
Figure 2-26  Speech Path Block Diagram (2/2)
ISWM
MUXMUXLC/TRKPIM0
IMG0 of LN2
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG1 of LN2
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG2 of LN2
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG3 of LN2
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
- Symbols -
:  Cable
:  Circuit card (ACT)
:  Circuit card (ST-BY)
:  Speech Path
TSW (in TSWM0/1) :  PH-SW12 TSW (in ISWM) :  PU-SW00
HSW:  PU-SW01
MUX:  PH-PC36
T
S
W
TSW/INTTSW 02
T
S
W020
021022
023024
025026
027028
02902A
02B02C
02D02E
02FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INTTSW 12
T
S
W120
121122
123124
125126
127128
12912A
12B12C
12D12E
12FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
W
HSW
T
S
W
TSW/INTTSW 03
T
S
W030
031032
033034
035036
037038
03903A
03B03C
03D03E
03FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INTTSW 13
T
S
W130
131132
133134
135136
137138
13913A
13B13C
13D13E
13FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
W
TSW/INTTSW/INT
TSW/INT
00800900A00B
00C00D00E00F
TSWM 0
  ( LN2)
M
U
X
TSW 00
M
U
XM
U
XM
U
X
TSW02
M
U
XM
U
XM
U
XM
U
XTSW/INT
M
U
XM
U
XM
U
XM
U
X
TSW 10
M
U
XM
U
XM
U
XM
U
X
TSW 12
M
U
X
TSW 01
M
U
XM
U
XM
U
X
TSW03
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 11
M
U
XM
U
XM
U
XM
U
X
TSW 13
TSW/INT
TSW/INTTSW/INT
TSW/INT000001002003 004005006007104105106107
100101102103
10810910A10B
10C10D10E10F
TSWM 1
  ( LN2)M
U
X
TSW 00
M
U
XM
U
XM
U
X
TSW02
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 10
M
U
XM
U
XM
U
XM
U
X
TSW 12
M
U
X
TSW 01
M
U
XM
U
XM
U
X
TSW03
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 11
M
U
XM
U
XM
U
XM
U
X
TSW 13
TSW/INT
TSW/INTTSW/INT
TSW/INT
TSW/INT
TSW/INTTSW/INT
TSW/INT000001002003 004005006007104105106107
100101102103
00800900A
00B 00C00D00E00F
10810910A10B
10C10D10E10F
MUXMUXLC/TRKPIM0
IMG0 of LN3
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG1 of LN3
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG2 of LN3
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
MUXMUXLC/TRKPIM0
IMG3 of LN3
PIM1MUXMUXLC/TRK
PIM2MUXMUXLC/TRK
PIM3MUXMUXLC/TRK
TSWM 0
  ( LN3)
M
U
X
TSW 00
M
U
XM
U
XM
U
X
TSW02
M
U
XM
U
XM
U
XM
U
XTSW/INT
M
U
XM
U
XM
U
XM
U
X
TSW 10
M
U
XM
U
XM
U
XM
U
X
TSW 12
M
U
X
TSW 01
M
U
XM
U
XM
U
X
TSW03
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 11
M
U
XM
U
XM
U
XM
U
X
TSW 13TSW/INTTSW/INT
TSW/INT TSW/INT
TSW/INTTSW/INT
TSW/INT
000 001002003 004005006007
00800900A00B
00C00D00E00F104105106107
100101102103
10810910A10B
10C10D10E10F
TSWM 1
  ( LN3)
M
U
X
TSW 00
M
U
XM
U
XM
U
X
TSW02
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 10
M
U
XM
U
XM
U
XM
U
X
TSW 12
M
U
X
TSW 01
M
U
XM
U
XM
U
X
TSW03
M
U
XM
U
XM
U
XM
U
X
M
U
XM
U
XM
U
XM
U
X
TSW 11
M
U
XM
U
XM
U
XM
U
X
TSW 13
TSW/INT
TSW/INTTSW/INT
TSW/INT
TSW/INT
TSW/INTTSW/INT
TSW/INT000001002003 004005006007104105106107
100101102103
00800900A00B
00C00D00E00F 10810910A10B
10C10D10E10F
HSW
T
S
W
TSW/INTTSW 00
T
S
W000001002003 004005006007 00800900A00B 00C00D00E00FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INTTSW 10
T
S
W100101102103 104105106107 10810910A10B10C10D10E10FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INTTSW 01
T
S
W010011012013 014015016017 01801901A01B 01C01D01E01FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
WT
S
W
TSW/INTTSW 11
T
S
W110111112113 114115116117 11811911A11B11C11D11E11FT
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
WT
S
W T
S
W T
S
W T
S
W T
S
W T
S
W
To TSWM0
    of LN0To TSWM1
    of LN0To TSWM0
    of LN1To TSWM1
    of LN1To TSWM0
    of LN0To TSWM1
    of LN0To TSWM0
    of LN1To TSWM1
    of LN1
This figure shows a block diagram of speech path. 
						

							CHAPTER 2 NDA-24307
Pag e 3 8
Issue 1
SYSTEM MAINTENANCE OUTLINE
Figure 2-27   Speech Path Range of Fault
MUX
A fault within this range
affects this module.
32ch
A fault within this range 
affects the circuit card.A fault within this range affects two slots.
PIM 3
A fault within this range
affects this module.
32ch
A fault within this range 
affects the circuit card.A fault within this range
affects two slots.
PIM 3
A fault within this range
affects this module.
32ch
A fault within this range 
affects the circuit card.A fault within this range
affects two slots.
PIM 3
A fault within this range
affects this module.
32ch
A fault within this range 
affects the circuit card.A fault within this range
affects two slots.
PIM 3
TSW
TSW/INT512ch
512ch
512ch
512ch
LC/TRK
LC/TRK
MUX
MUX
MUX
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
: Circuit Card : Possible fault range to be affected : Speech Path
Symbols 
						

							NDA-24307 CHAPTER 2
Page 39
Issue 1
SYSTEM MAINTENANCE OUTLINE
2.8 Explanation of Terms
C-Level Infinite Loop
The program repeatedly executes specific routines due to a fault of the main memory, data destruction,
etc. The program is not able to be processed normally. This faulty condition is referred to as Program
Infinite Loop. C-Level infinite loop is a state where a clock-level program, which runs under clock
interrupt disable state, is in an infinite loop status.
B-Level Infinite Loop
This is a state where a program infinite loop has occurred during a connection processing and the
connection for the next call is not able to be processed.
PM (Port Microprocessor)
Each line/trunk card mounted in the PIM is equipped with a processor called Port Microprocessor
(PM), which continuously supervises the lines/trunks.
Ready Error
For acknowledging the connection between the CPU and a circuit card, an interface signal called
Ready Signal is used. When the CPU has accessed a specific circuit card and the normality of the
connection is acknowledged, the Ready Signal is returned to the CPU within 6 µs. If the Ready signal
is not returned to the CPU within 6 µs after access, the situation is referred to as Ready Error.
Parity Error
For confirming the normality of data transfer between the CPU and the circuit card under the control
of the CPU, parity check is made. When an error is detected in a parity check, it is referred to as Parity
Error. Parity check means to confirm the normality of data by adding an error detecting parity bit to
a set of data to be transferred.
When a set of data is transferred, a parity bit is added to the data so that the data has an even-number
of “1” bits (it is referred to as Even Parity). When there is an odd-number of “1” bits in the received
one set of data, it is detected as an error.
Monitor Restart
Monitor restart processing suspends current processings in progress without applying any hardware
controlling, allowing the system to restart its operations from the monitor program.
The system abandons only the processings of the calls being handled by the program, and maintains
all the connections that have already been established.
Circuit Card Front Initializing Restart
The whole system is forcibly initialized. However, the initialization varies with the setting of the
SENSE switch on the DSP of CPU (see Table 2-2). 
						

							CHAPTER 2 NDA-24307
Pag e 4 0
Issue 1
SYSTEM MAINTENANCE OUTLINE
PM (Line/Trunk Card) Make-Busy Restart
In this processing, the faulty PM (Line/Trunk Card) is isolated from the system and, at the same time,
the calls associated with that faulty PM (Line/Trunk Card) are released. No calls related to the faulty
PM (Line/Trunk Card) are processed and the system normally runs without the faulty PM (Line/Trunk
Card).
Data Copy Restart
In a system of dual CPU configuration, the RAM memory (including the data memory) is copied from
the ACT side CPU into the STBY side CPU, and ACT/STBY is changed over and monitor restart is
executed.
In the case of this restart processing, only the ACT side CPU and the STBY side CPU are changed
over without any effect on the current connections. However, no call processings are executed while
the restart processing is in progress (from copying until the end of the changeover).
Table 2-2  Kinds of Circuit Card Front Restart
SENSE (0~F) KIND OF RESTART REMARKS
1 DM Clear Restart
2 DM Load Restart When the system is in operation
5 OAI Memory Clear Restart
C OFF-line Restart 
						

							NDA-24307 CHAPTER 2
Page 41
Issue 1
SYSTEM MAINTENANCE OUTLINE
3. HOW TO READ PRECAUTIONS, DIAGNOSTIC, AND FAULT REPAIR INFORMATION
3.1 Precaution about Diagnostic Procedure/Fault Repair Procedure
When performing diagnostic procedures/fault repair procedures, be aware of the following actions:
(1) When replacing a circuit card with a spare, handle the circuit card using the Field Service Kit.
(a) To protect the circuit card from static electricity, wear a wrist strap before handling the circuit card.
(b) Before extracting the circuit card from its mounting slot, set its MB switch to the UP side (ON).
(2)When holding a circuit card by hand, wear gloves and be careful not to touch mounted parts, gold-
plated terminal, etc., on the circuit card.
The 3M
 Model 8012 Portable Field Service Kit, shown in Figure 2-28, is recommended as an effective
countermeasure against static electricity.
Figure 2-28   3M® Model 8012 Portable Field Service Kit
Wrist StrapPlace the Circuit
Card on a
conductive sheet. Connect ground wire to the Earth
terminal of the Module Group.
Note:3M is a registered trademark of Minnesota Mining and Manufacturing, Inc. 
						

							CHAPTER 2 NDA-24307
Pag e 4 2
Issue 1
SYSTEM MAINTENANCE OUTLINE
Figure 2-29   How to Hold a Circuit Card
(3) When a circuit card appears to be faulty, check the following items before replacing it with a spare:
(a) Poor connector contact at the circuit card may be responsible for the fault. Repeat insertion and
extraction of the circuit card a few times. Clean the connector portion, and recheck for proper
operation.
(b) Check the lead wires of vertically-mounted parts (resistors, capacitors, etc.) to ensure they have not
shorted each other or broken.
(c) Check the back side of the circuit card to see if there is any short-circuited soldered portion, or
modified cross connection wires erroneously left unconnected.
(d) Check the ROMs to ensure proper seating in the IC socket. Figure 2-30 shows a leg that is bent and
not set in the socket.
Figure 2-30   How to Set the ROM in IC Socket
12
34
OFF12
34
567
8
OFF
12
34
5
67
8
OFF
12
34
5
67
8
OFF
12
34
5
67
8
OFF
12
34
OFF
12
34
OFF
12
34
567
8
OFF12
34
5
67
8
OFF12
34
5
67
8
OFF
12
34
5
67
8
OFF
Card Puller Tab Circuit Card Circuit Card
Plastic BagGold Plated Terminal
Note
Note:Do not touch the Gold Plated Terminal with bare hands.
A pin is bent, not 
inserted in the socket.
ROM
SOCKET