NEC Neax 2400 Imx System Operations And Maintenance Manual

							CHAPTER 2 NDA-24238
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Revision 3.0
SYSTEM MAINTENANCE OUTLINE
2.4 System Messages
System messages display during routine diagnosis, system operation status controlling, and fault occur-
rence. Figure 2-12 shows an example of a system message.
Refer to Chapter 3 for details on each message.
Figure 2-12   System Message Example (1)           SYSTEM MESSAGE 3-E SUP LOCK UP FAILURE (TEMPORARY)
(2) NEC TOKYO                  JUL 24 09:35
(3) LP00-0-ACT
(4)
4:0000 0000 0000 0000      5:0000 0000 0000 0000      6:0000 0000 0000 0000 1:1102 0000 0000 0000      2:0000 0000 0000 0000      3:0000 0000 0000 0000
7:0000 0000 0000 0000      8:0000 0000 0000 0000      9:0000 0000 0000 0000
Meaning:
(1)    :    SYSTEM MESSAGE 3-E     SUP     LOCK-UP FAILURE (TEMPORARY)
Meaning of the message
System Message Level
(Indicated by Alarm Lamp)Note
System Message Number
(2)   :   Office Name, Date and Time
(3)   :   LP00-0-ACT
ACT/STBY indication for dual systems
Faulty processor/Related processor 
No.0/No.1 system indication for dual systems
(4)   :   Message detail data (notation by hexadecimal numbers)
Note:There are four kinds of alarm information to be indicated by alarm lamps: MN,
MJ, SUP, and No Indication. 
						

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2.5 Fault Detecting Function
The system finds a fault by its fault detecting circuit and the fault detecting program. Once a fault occurs,
the system initiates a remedial action such as system changeover, make-busy setting, or restart processing
by the automatic diagnosis function. This action reduces the influence of the fault so that system servicing
may be minimized. The result of the process taken and the fault situation are indicated for equipment con-
cerned.
Among the faults, those related to speech path (noise, one-way speech, speech inability, etc.) are not de-
tectable. Since these fault reports are to be obtained from a station or operator, periodic trunk tests must
be performed without failure to detect the faults related to speech path.
Figure 2-13 shows an outline of fault detection, and Figure 2-14 shows a block diagram of fault detection.
Figure 2-13   Fault Detection General Diagram
Fault Occurrence
IndicationInformation
Collection and DiagnosisExample of Faults
IOC
CPU
EMA
Display of
System Messages
Indication of
Alarm Lamps
on TOPU
Fault of line/trunk card
TSW write failure,
Fault of clocks, etc.
Abnormal temperature,
power supply failure,
fuse blowing, etc., within
the equipment frame
NECNEAX 2400 IMS


 
						

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SYSTEM MAINTENANCE OUTLINE
Figure 2-14   Fault Detection Block Diagram
TSW/INT
LC/TRK
MUX
CPU
EMA
PWR
DLKC
GT
To MAT,
Printer, etc.
Alarm Lamps on TOPU
Thermal Reed Relay
TSWM
RDY
Clock
etc.
Howler
Ringing
Circuit
Fault
Note
PWR Supply
Failure,
Fuse Blown
Ready
IOC
Symbols
: Circuit Card
: Main faults to be detected
: Speech path
: Flow of fault information
SYMBOL NAME SYMBOL NAME
CPU
EMA
IOC
LC/TRK
GT
PWRDLKC
INT
TSW
MUX
TSWM Central Processing Unit
Emergency Alarm Controller
I/O Controller
Line/Trunk
Gate
Power SupplyData Link Controller
Speech Path Control Interface
Time Division Switch
Multiplexer
Time Division Switch Module
Information
monitor C-level
Firmware
   Fault
Note:MJ, MN fault
Power, Fuse blown fault
Temperature, CPU fault
Speech Path System fault (SPE)
RGU, Howler fault
PFT fault
CPU Clock fault
RDY
Clock
Write
etc. 
						

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SYSTEM MAINTENANCE OUTLINE
(a) Main Faults
Faults that may occur in the system can be generally categorized into Processor System Fault, Speech
Path System Fault, Line/Trunk Fault, etc.
 Processor System Fault
The CPU alarm detecting circuit continuously monitors whether the CPU is working normally. If
a fault is detected, the CPU calls up the diagnostic program, which identifies the cause of the fault
and determines whether the fault is temporary or permanent. When the fault affects system oper-
ations, Active/Standby status of the CPU is changed over (provided that the system has dual con-
figuration).
 Bus System Fault
The CPU transfers line/trunk card control information to the associated peripheral circuits via IO
Bus. When a parity error is detected in the transfer data or when the required information cannot
be transferred from a circuit card, the CPU identifies the cause of the fault, changes over the CPU
so that system operation is not affected, and executes restart processing.
 Speech Path Fault
The CPU monitors the operating status of the TSW card, the occurrence of errors in writing data
to the switch memory, and the basic clocks supplied to the speech path. Upon detecting a fault, the
CPU identifies the cause of the fault, determines whether the fault is temporary or permanent, and
executes required processing such as changeover of the TSW card.
Others
The alarm detecting circuit on the EMA card continuously monitors the occurrence of faults in the
PWR supply cards, such as abnormal temperatures within the equipment frame, and lights the
alarm lamp on the TOPU when a fault is detected.
(b) Lamp Indications on the TOPU
When a fault occurs, the corresponding lamp on the TOPU indicates the location of the fault. For the
meaning of each lamp indication, refer to Chapter 6. 
						

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SYSTEM MAINTENANCE OUTLINE
2.6 Range of Faults Specification
(1) Upon receiving a fault report from a station user or an operator, the technician can assume a faulty card
exists if the range to be affected by the fault can be determined. For the detailed procedure, refer to Chap-
ter 5. Use the following actions to check the MDF:
(a) Check the LENS of the reporter (Station or ATTCON/DESKCON).
(b) Check other circuits of the circuit card in which the reporter (station line or ATTCON/DESKCON)
is located.
(c) Check the other groups (other circuit cards mounted in the same module) in the module in which the
reporter is located.
(d) Check lines in each of the other modules on the basis of plural lines.
(2) If the fault cannot be detected by the system (a fault related to the speech path such as noise during speech,
one-way speech, speech inability), the range of (a) through (d) (itemized above) should be limited.
(3) When a major fault is detected in the dual systems, the CPU or TSW system automatically changes over
if the fault range is (c) and (d). In this case, the whole module involved is placed into make-busy status
even if the fault is partial, and the station lines currently operating normally become faulty status. Diag-
nose the fault from the content of the system message displayed and repair the fault as required.
(4) When limiting the range of faults, consider the system circuitry that consists of the control (see Figure 2-
16, where CPU 0 is active) and speech path systems (see Figure 2-17).
(5) As seen from the block diagrams in Figure 2-15 through Figure 2-18, if a fault occurs within the common
portions to be controlled, all other associated portions are affected by that fault occurrence. If the range
of faults is outside PIM fault, CPU/TSW system changeover is executed (only when the fault is detectable
by the system). 
						

							NDA-24238 CHAPTER 2
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SYSTEM MAINTENANCE OUTLINE
Figure 2-15   General System Block Diagram
CPU 0
To MUXTo MUX
To MUX (IMG2)
To MUX (IMG2)
To MUX (IMG3)
To MUX (IMG3)
IMG0
TSWM
LPM
MISC I/O BUS
MISC I/O BUS MISC I/O BUS
01
E1/DS1
with
Fusion LinkE1/DS1
with
Fusion Link SERIAL BUS
PM BUS
PM BUS
PM BUS
PM BUSPM BUS
PM BUS
PM BUS
PM BUS
T
S
W
 I
 /
O
B
U
S
0
RS-232C
10 BASE-T 10 BASE-T 10 BASE-T
G
T
U
S
Symbols
EMA:  PH-PC40      ISAGT:  PZ-GT13       LANI:  PZ-PC19      GT:  PH-GT09                        IOC:  PH-IO24
TSW:  PH-SW12      DLKC:  PH-PC20       MUX:  PH-PC36      PLO:  PH-CK16/17/16-A/17-A
LC/TRKLC/TRKMUX
MUX
LC/TRKLC/TRKMUX
LC/TRKLC/TRKMUX
DTIFCHLC/TRK
MUX
MUX
MUX
MUXLC/TRKLC/TRK
LC/TRKLC/TRK
LC/TRKLC/TRK
DTIFCHLC/TRK
TSW 00TSW 10
TSW 01
TSW 11
TSW 02
TSW 12
TSW 03TSW 13
PLO 0PLO 1
MISC
GT 1GT 0
DLKC 0DLKC 1
MAT
MATAP
HUB
HUBHUB
EMA
MISC
IOC
ISAGT
LANILANI
CPU 1
ISAGT
LANILANI
G
T
B
U
S BT
S
W
 I
 /
O
B
U
S
0
: Circuit Card 
						

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SYSTEM MAINTENANCE OUTLINE
Figure 2-16   CPU Controlling Block Diagram
LPM
EMAIOC /
MISC
ISAGT 0
LANI
PWR
PWR
CPU 0
MEMORY
PCI BUSISA BUS
CPU board CPR
CPU clock
   CPR
(ST-BY)
Reset Signal
MISC BUS
MISC BUS
ISAGT 1 T
MT
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
IMG0
PIM 3
PIM 2
PIM 1
PIM 0
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
IMG1
PIM 3
PIM 2
PIM 1
PIM 0
Note 1:  The circuit cards, drawn by dotted lines, indicate they are in STBY state. These cards (TSW, MUX and
               DLKC) are totally  changed over to the ACT mode, when the MBR key of the active GT (PH-GT09) card is 
               once flipped. However, PLO (PH-CK16/17/16-A/17-A) is independent and not affected by the development.
Symbols
          :  Controlling Routes of CPU                         :  Cable
          :  Circuit card (active)                  :  Circuit card (STBY)
            :  External Cable                  :  Clock Oscillator
            :  Signral
EMA:      PH-PC40                      ISAGT:     PZ-GT13
LANI:      PZ-PC19                      GT:           PH-GT09
IOC:        PH-IO24                       TSW:        PH-SW12
DLKC:     PH-PC20                      PLO:         PH-CK16/17/16-A/17-A
MUX:      PH-PC36 
TSWM  
TSW 00TSW 10TSW 11TSW 01
PLO 0PLO 1
DLKC 1DLKC 0DLKC 1
GT 1
GT 0
MISC BUS
MISC BUS
MISC BUS
MISC BUSMISC BUS MISC BUS
TSW
    02TSW 
    03TSW
    13TSW
    12
To IMG 2To IMG 3To IMG 3 To IMG 2
IOP1
IOP0
TSW/INT TSW/INT TSW/INTTSW/INT
M
U
X003
M
U
X002
M
U
X001
M
U
X000
M
U
X013
M
U
X012
M
U
X011
M
U
X010
M
U
X100
M
U
X101
M
U
X102
M
U
X103
M
U
X110
M
U
X111
M
U
X112
M
U
X113
  TSW
   /INT  TSW
   /INTTSW
 /INT TSW
 /INT
Note 1
Note 2:  If the ACT/STBY of CPU is once changed over, the system of GT (in TSWM) also changes over.
Note 3:  Though an external cable is physically connected between ISAGT0 and GT1, the actual control signal is
sent/received only between ISAGT0 and GT0. This is because GT0 and GT1 are having a multiple connection

on the backboard side. (Refer to Chapter 6, Section 12.)
Note 3
Note 2

BUS
TSW I/O BUSTSW I/O  
						

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SYSTEM MAINTENANCE OUTLINE
Figure 2-16  CPU Controlling Block Diagram (Continued)
LPM
EMAIOC /
MISC
ISAGT 0
LANI
PWR
PWR
CPU 0
MEMORY
PCI BUSISA BUS
CPU board CPR
CPU clock
   CPR
(ST-BY)
Reset Signal
MISC BUS
MISC BUS
ISAGT 1 T
MT
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
IMG2
PIM 3
PIM 2
PIM 1
PIM 0
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
IMG3
PIM 3
PIM 2
PIM 1
PIM 0
Note 1:  The circuit cards, drawn by dotted lines, indicate they are in STBY state. These cards (TSW, MUX and
               DLKC) are totally changed over to the ACT mode, when the MBR key of the active GT (PH-GT09) card is 
               once flipped. However, PLO (PH-CK16/17/16-A/17-A) is independent and not affected by the development.
Symbols
          :  Controlling Routes of CPU                    :  Cable
          :  Circuit card (active)              :  Circuit card (STBY)
            :  External Cable                  :  Clock Oscillator
            :  Signral
EMA:      PH-PC40                      ISAGT:     PZ-GT13
LANI:      PZ-PC19                      GT:           PH-GT09
IOC:        PH-IO24                       TSW:        PH-SW12
DLKC:     PH-PC20                      PLO:         PH-CK16/17/16-A/17-A
MUX:      PH-PC36 
TSWM  
TSW 02TSW 12TSW 13TSW 03
PLO 0PLO 1
DLKC 1DLKC 0DLKC 1
GT 1
GT 0
MISC BUS
MISC BUS
MISC BUS
MISC BUSMISC BUS MISC BUSTSW I/O TSW I/O 
TSW
    00TSW 
    01TSW
    11TSW
    10
To IMG 0To IMG 1To IMG 1 To IMG 0
IOP1
IOP0
TSW/INT TSW/INT TSW/INTTSW/INT
M
U
X023
M
U
X022
M
U
X021
M
U
X020
M
U
X033
M
U
X032
M
U
X031
M
U
X030
M
U
X120
M
U
X121
M
U
X122
M
U
X123
M
U
X130
M
U
X131
M
U
X132
M
U
X133
  TSW
   /INT  TSW
   /INT  TSW
   /INT   TSW
   /INT
Note 1
Note 2:  If the ACT/STBY of CPU is once changed over, the system of GT (in TSWM) also changes over.
Note 3:  Though an external cable is physically connected between ISAGT0 and GT1, the actual control signal is
sent/received only between ISAGT0 and GT0. This is because GT0 and GT1 are having a multiple connection

on the backboard side. (Refer to Chapter 6, Section 12.)
BUSBUS

Note 3
Note 2


 
						

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SYSTEM MAINTENANCE OUTLINE
Figure 2-17   Speech Path Block Diagram
IMG0
TSW
02
To IMG2
TSWM
TSW 00
TSW/INTMUX 003
MUX 002
MUX 001
MUX 000
PIM 3
LC/TRK
MUX
Symbols
          :  Speech Path 
          :  Circuit Card (active)
TSW:  PH-SW12
MUX:  PH-PC36 
LC/TRKLC/TRK
MUX
PIM 2
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 1
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 0
LC/TRK
MUX
LC/TRKLC/TRK
MUX
IMG1
PIM 3
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 2
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 1
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 0
LC/TRK
MUX
LC/TRKLC/TRK
MUX
 :  Circuit Card (STBY)  :  Cable
TSW 01
TSW/INTMUX 013
MUX 012
MUX 011
MUX 010
TSW 10
TSW/INTMUX 100
MUX 101
MUX 102
MUX 103
TSW 11
TSW/INTMUX 110
MUX 111
MUX 112
MUX 113
TSW/
INT
TSW
12
To IMG2
TSW/
INT
TSW
03
To IMG3
TSW/
INT
TSW
13
To IMG3
TSW/
INTLVDS (Low Voltage Differential Signaling) 
						

							NDA-24238 CHAPTER 2
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SYSTEM MAINTENANCE OUTLINE
Figure 2-17  Speech Path Block Diagram (Continued)
IMG2
TSW
00
To IMG0
TSWM
TSW 02
TSW/INTMUX 023
MUX 022
MUX 021
MUX 020
PIM 3
LC/TRK
MUX
Symbols
          :  Speech Path 
          :  Circuit Card (Active)
TSW:  PH-SW12
MUX:  PH-PC36 
LC/TRKLC/TRK
MUX
PIM 2
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 1
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 0
LC/TRK
MUX
LC/TRKLC/TRK
MUX
IMG3
PIM 3
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 2
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 1
LC/TRK
MUX
LC/TRKLC/TRK
MUX
PIM 0
LC/TRK
MUX
LC/TRKLC/TRK
MUX
 :  Circuit Card (STBY)  :  Cable
TSW 03
TSW/INTMUX 033
MUX 032
MUX 031
MUX 030
TSW 12
TSW/INTMUX 120
MUX 121
MUX 122
MUX 123
TSW 13
TSW/INTMUX 130
MUX 131
MUX 132
MUX 133
TSW/
INT
TSW
10
To IMG0
TSW/
INT
TSW
01
To IMG1
TSW/
INT
TSW
11
To IMG1
TSW/
INTLVDS (Low Voltage Differential Signaling)