NEC Mcu 5000a Multipoint Control Unit Equipment Manual
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NECA 340-414-100 Revision 2.0Page 39 MCU 5000A Multipoint Control Unit General Description Manual F: A CODEC Unit 4.20 The A CODEC unit, which accommodates four audio channels per unit. Two A CODEC units can be installed in a MCU 5000A subrack (Total eight channels per subrack). (1) The received audio coding signal (64/56/48 kbps, µ -law PCM or SB- ADPCM) from multiplexing/demultiplexing part (EC H221 MUX unit) is decoded to PCM signal (8 kHz×14 bit or 16 kHz×16 bit). The output level is adjusted with attenuator, and is sent to the audio summing (A SUM) unit as the received audio decoding signal. (2) The received audio decoding signal is subtracted from the added PCM signal from the audio summing part (A SUM unit), and the summed signal is compress-coded with 64/56/48 kbps or µ -law PCM/SB- ADPCM. The compress-coded signal is sent to the multiplexing/ demultiplexing part (EC H221 MUX unit). Functions (1) Audio Signal Decoding The received audio coding signal (64/56/48 kbps, µ -law PCM or SB- ADPCM) from multiplexing/demultiplexing part (EC H221 MUX unit) is decoded to PCM signal (8 kHz×14 bit or 16 kHz×16 bit). (2) Audio Level Detection The decoded PCM signal is smoothed for a time (called “frame”), and the mean power as the result of the smoothing is sent to the audio sum part (A SUM unit) and control part (M CONT unit) as audio level. (1 frame: 20.0 msec, frame position free) (3) Voice Detection This unit verifies with audio level whether the incoming audio signal is in voice or non-voice frame, and sends it to the audio sum part (A SUM unit) and control part (M CONT unit). The threshold level can be set between -36 and -12 dBm by the M CONT unit and dip switch. (4) Talker Detection The unit send talker detection signal, which is made voice detection signal with forward/backward guard time. Forward guard time can be set the 10 to 630 ms, and backward guard time can be set the 10 to 310 ms by dip switch and M CONT unit. (5) Load Insertion As the talker information from A SUM unit. The unit inserts load to the coded PCM signal. (6) Audio Signal Substructing The received audio decoding signal is subtracted from the summing PCM signal in the audio sum part (A SUM unit).
Page 40NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit (7) Audio Signal Coding The subtracted PCM signal is compress-coded with 64/56/48 kbps, µ -law PCM or SB-ADPCM. This signal is sent to the multiplexing/ demultiplexing part (EC H221 MUX unit) as send audio coding signal. (8) Muting When receiving the muting signal from the control part (M CONT unit), the receive audio decoding signal (MUTE 1) or substructed summing PCM signal (MUTE 2) is muted. (9) Test Tone Output The test tone is inserted to the receive audio decoding signal (TONE 1) or substructed summing PCM signal (TONE 2) by specifying the level signal (4 stages) and frequency number (4 stages) from the control part (M CONT unit). (10) Loopback The remote and local loopback are simultaneously performed by setting loopback from the control part (M CONT unit). Note: These functions above are independent in every channel. The different function can be set per each channel. Table 4-8 shows the voice signal level setting value, and Fig. 4-10 shows the block diagram of A CODEC unit. Table 4-8: Voice Signal Level Setting Value µ-law PCM SB-ADPCM Standard Level4WS 0 dBr 0 dBr 4WR 0 dBr 0 dBr Level Range4WS + 7.5 to -8 dBr +4 to -11.5 dBr 4WR +4 to -11.5 dBr +2 to -13.5 dBr Standard Level -9 dBrm -9 dBrm (Maximum Average) (4.5 VU) (Voice Signal Level) Peak Factor 9 dB (3 s) 15 dB Overload Allowance 3 dB 3 dB Overload Level +3 dBm +9 dBm Overload Point +3 dBm 0 (G.711) +9 dBm 0 (G.722)
NECA 340-414-100 Revision 2.0Page 41 MCU 5000A Multipoint Control Unit General Description Manual Figure 4-10: Block Diagram of A CODEC Unit SB-ADPCM DECODER 64 kbps m-Law PCM DECODER SB-ADPCM DECODER 64 kbps m-Law PCM DECODERVOICE LEVEL CALCULATIONVOICE DETECTIONSPEECH DETECTIONM U X AT T E N U AT I O N DELAY + - + TEST TONE OSCILLATOR (+5v) (+5v) 64/56 kbps VOICE DATA (RECEIVE) 64/56 kbps VOICE DATA (SEND)LOOP MUTE1TONE1 THR BP FPVOICE POW INFORMATION DATA VOICE POWER INFORMATION DATA AT T E N UAT I O N LINEAR VOICE DATA (RECEIVER) LINEAR VOICE DATA (SEND) FRQ LEV TONE2 ASEL MUTE2
Page 42 NECA 340 -41 4-1 00 Revisi on 2.0 General Descr ipt ion Manual MCU 5000A Mult ipoint Con trol Unit G: A SUM Unit General
NECA 340-414-100 Revision 2.0Page 43 MCU 5000A Multipoint Control Unit General Description Manual Figure 4-11: Block Diagram of Voice Signal Process 1 LOAD CONTROLLER TA L K E R IDENTIFIER MESSAGE TONE OSCILLATOR D/A + + + + + + + + TO A CODECTO M CONT VOICE/NON-VOICE CH 1 VOICE/NON-VOICE CH 8 LOADING VALUE CH 1 LOADING VALUE CH 8 TALKER/NON-TALKER CH 1 TALKER/NON-TALKER CH 8 CH 1 PCMIN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT CH 2 PCM CH 3 PCM CH 4 PCM CH 5 PCM CH 6 PCM CH 7 PCM CH 8 PCM FROM CONF BCASADE CONNECTION CH SPECIFICATION FORCED SPECIFICATION CH NO. MAIN TALKER CHANNEL M TONE MONITOR OUT
Page 44NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit Figure 4-12: Block Diagram of Voice Signal Process 2 TALK DECISION LOAD CONTROL S TALK DECISION LOAD CONTROL S - DEC DOCVD(MDRn) CODED VOICE SIGNAL INPUT (MDRn) CODED VOICE SIGNAL OUTPUTVOICE/NON-VOICE TALKING/NON-TALKING (APD) A.T.T. VALUE (AAD) DECODED VOICE OUTPUT (LDR) SUM VOICE SIGNAL INPUT (LSD) CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 CH 8MUX DEM MUX DEM A CODEC #2 (E32-441-Y1438-0A00)A CODEC #1 (E32-441-Y1438-0A00) TELECONFERENCE A MAIN TALKER CH TELECONFERENCE A CH EXCEPT TALKER CH TELECONFERENCE B MAIN TALKER CH TELECONFERENCE B CH EXCEPT TALKER CH
NECA 340-414-100 Revision 2.0Page 45 MCU 5000A Multipoint Control Unit General Description Manual H: PG/SIO Unit General 4.22 This unit generates the clock which is locked the phases of the internal clock within MCU 5000A and external clock extracted from the line by LIF unit. The four RS-232C interface ports are provided. Fig. 4-13 shows the Block Diagram of PG/SIO unit. Functions (1) Clock Phase Locking (PLO: Phase Locked Oscillator) Each internal clock phase (1.544 MHz, 4.096 MHz, or 10.752 MHz) generated in this unit is locked for the external clock from the line in LIF unit. The locked clock signal is sent to the other units. (Internal clock duty is 50%.) When the loss of external clock or internal clock phase slip etc. occur, this unit requests the troubleclearing to the master CPU in M CONT unit. The system clock is generated with 4.0966 MHz above, and sent it to the other units. (2) Console Communication Four RS-232C interfaces are provided for M CONT unit I/O interface for console communication. The communication condition for the RS-232C interface is determined in accordance with the parameters in the serial controller (MB89371A) of this unit set by master CPU on the M CONT unit. Table 4-9 shows the parameter for RS-232C interface. (3) Interrupting Control The interruption (RS-232C sending/receiving interruption) in this unit and the interruption (main talker change) in the A SUM unit are collected to the interrupting controller, and the interruption is performed to the M CONT unit. Table 4-9: RS-232C Parameter PARAMETER FUNCTION Synchronization mode Start-stop Synchronization Mode Baud Rate 1200/2400/4800/9600 bps Character Bit Length 8 bit Stop Bit Length 1 bit Parity Check Null Loopback Function from SD to RD Loopback in IC inside
Page 46NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit Figure 4-13: Block Diagram of PG/SIO Unit 4 44 4 SERIAL CONTROLLER SERIAL CONTROLLER INTERRUPT CONTROLLER INTERRUPT CONTROLLER 1.544 MHz PLO CIRCUIT 4.096 MHz PLO CIRCUIT 10.752 MHz PLO CIRCUIT OSCILLATORSEL CLK LOSS DETECTOR 1.5M LIF UNIT1.5M LIF UNIT M CONT UNITCPU INF CLK LOSS SLIP1 SLIP2 SLIP3 CH8CH7 CH6 CH5 CH4 CH3 CH2 CH1LINE LINECPU BUSPG/SIO PLO: PHASE LOCKED OSCILLATORRS-232C CH4 RS-232C CH4 RS-232C CH4 RS-232C CH4 INTO INTERRUPTION REQUEST 1.544 MHz 4.096MHz OCTET FRAME MF 10.752 MHz
NECA 340-414-100 Revision 2.0Page 47 MCU 5000A Multipoint Control Unit General Description Manual I: M CONT Unit General 4.23 The M CONT unit consists of V53CPU (UPD70236), 256 kbytes ROM (UPD27C1001×2), 3.6 Mbytes RAM (UPD424400×8), (UPD431000×2),1 Mbytes Memory Card, and Real-time Clock (RTC-62421) etc., and which controls the MCU 5000A. The interruption and serial communication control operation are performed with the V53 ICU or SCU. Fig. 4-14 shows the Block Diagram of M CONT unit. Functions (1) MPU : V53 (UPD70236R-8, 8 MHz) (2) Memory : ROM 256 kbytes (UPD27C1001AD×2) DRAM 3.5 Mbytes (UPD424400×8) SRAM 128 kbytes (UPD431000×2) Memory Card1 Mbytes (3) Oscillator : Crystal oscillator (31.9488 MHz) (4) Real-time Clock : RTC-62421 (5) RS-232C Controller : V53 internal peripheral (UPD71051 sub set) (Program test usage) (6) Timer/Counter : V53 internal peripheral (UPD71054 sub set) (7) Interruption Detector: V53 internal peripheral (UPD71059 sub set) (8) DMA : V53 internal peripheral (UPD71071 sub set)
Page 48NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit Figure 4-14: Block Diagram of M CONT Unit OSC 31.9488 MHz CLOCK IN UPD70236 (V53) INT SCUTTL/ RS-232C CN3 UPD4711A ADDRESS DEC RAM CARD SRAM X 2 (128 KB) DRAM X 2 (3.5 MB) ROM X 2 (256 KB)UPD431000 UPD424400 UPD27C1001AD ADDRESS ADDRESS BUS DATA DATA BUS CONT CONTROL BUS REAL TIME CLOCK SYS BUS