NEC Mcu 5000a Multipoint Control Unit Equipment Manual
Have a look at the manual NEC Mcu 5000a Multipoint Control Unit Equipment Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 1168 NEC manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
NECA 340-414-100 Revision 2.0Page 29 MCU 5000A Multipoint Control Unit General Description Manual (2) Table 4-5 and Fig. 4-4 show RS-422 LIF Connector pin assignment. Figure 4-4: RS-422 LIF (CH1 to CH16) Connector Pin Assignment Table 4-5: RS-422 LIF (CH1 to CH16) Signal Assignment PIN NO. SIGNAL NAME I /O REMARKS PIN NO. SIGNAL NAME I /O REMARKS 1 SHIELD Cable shield 9 T (B)+ OUT Transmitting (B) 2 T (A)_ OUT Transmitting Data (A) 10 C (B)+ OUT Control (B) 3 C (A)_ OUT Control (A) 11 R (B)+ IN Receiving (B) 4 R (A)_ IN Receiving Data (A) 12 I (B)+ IN Indication (B) 5 I (A)_ IN Indication (A) 13 S (B)+ IN Timing (B IN) 6 S (A)_ IN Timing (A IN) 14 S (B)+ OUT Timing (B OUT) 7 S (A)_ OUT Timing (A OUT) 15 FG Frame Ground 8 SG Signal ground 81 9 15
Page 30NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit (3) Fig. 4-5 shows the Block diagram of RS-422 LIF unit. Figure 4-5: Block Diagram of RS-422 LIF Unit MTSCLIF LEVEL CONV RATE CONV LIF LEVEL CONV RATE CONV LIF LEVEL CONV RATE CONV LIF LEVEL CONV RATE CONV IN OUT 14 14 OUT IN 14 14 IN OUT 14 14 OUT IN 14 14 IN OUT 14 14 OUT IN 14 14 IN OUT 14 14 OUT IN 14 14 DELAY & MUXH221 SYNC DET H221 SYNC DET DELAY & MUXH221 SYNC DET H221 SYNC DET TERMINAL1 B1 + B2 MULTI FRAME TS31 MULTI FRAME TS31 TERMINAL2 B1 + B2 B1 B2 B3 B4 IN1 OUT1 IN2 OUT2 IN3 OUT3 IN4 OUT4 SYNC SYSTEMSYSTEM SYNC OUT1 OUT2 OUT3 OUT4 IN1 IN2 IN3 IN4 EC H221 MUX (LD S/R) POINT-TO- POINT LINE BUS (LB) IN OUT IN OUT IN OUT IN OUT PORT4PORT3PORT2PORT1 T E R M I N A L 1 T E R M I N A L 2 MTSC LIF LEVEL CONV RATE CONV LIF LEVEL CONV RATE CONV LIF LEVEL CONV RATE CONV LIF LEVEL CONV RATE CONV IN OUT 14 14 OUT IN 14 14 IN OUT 14 14 OUT IN 14 14 IN OUT 14 14 OUT IN 14 14 IN OUT 14 14 OUT IN 14 14 DELAY & MUXH221 SYNC DET H221 SYNC DET DELAY & MUXH221 SYNC DET H221 SYNC DET EC H221 MUX (LD S/R) POINT-TO- POINT LINE BUS (LB) IN OUT IN OUT IN OUT IN OUT PORT4PORT3PORT2PORT1T E R M I N A L 1 T E R M I N A L 3 (a) 2 Port for 1 Terminal [2 x B] NOT USED NOT USEDSYNC IN1 IN2 IN3 IN4SYNC OUT1 OUT2 OUT3 OUT4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 44 4 4 4 4 4 4 48 88 8 8 8 8 8 4 4 4 44 44 4 T E R M I N A L 2 T E R M I N A L 44 (b) 1 Port for 1 Terminal
NECA 340-414-100 Revision 2.0Page 31 MCU 5000A Multipoint Control Unit General Description Manual C: H0-INF Unit General 4.10 The H0-INF unit receives 1.5 Mbps data signal from ISDN line. After extracting the clock pulse in IPAT, bipolar to unipolar conversion is executed, and sends it to ACFA. ACFA performs frame synchronization, internal data high-way bit rate conversion, and detection of transmission line failure for the data signal, and sends it to MTSC. MTSC performs the line setting with time slot (1 time slot per 64 kbps) to output the data signal of two ports to the multipoint teleconference data bus (LMB) and point-to-point teleconference data bus (LB). 4.11 This unit sends the receive data signal for D ch control to PIIFC from the receive data bus between ACFA and MTSC. PIIFC protocol-converts the receive data signal of the D ch (time slot 24) specified at HSCX. 4.12 The port to which the data signal from individual teleconference data bus is sent is specified by MTSC, and sends the data signal to ACFA. ACFA performs the bit rate conversion from internal data high-way (2 Mbps) to line rate (1.5 Mbps) and frame addition, and sends it to IPAT. IPAT sends the data signal, which is converted unipolar to bipolar, to ISDN transmission line. 4.13 The data signal of time slot 24 only from HSCX of PIIFC in D ch is multiplexed, and sends the multiplexed signal to the transmission data path from MTSC to ACFA. Furthermore, the loopback for line side and within the equipment can be executed independently, and also the LED lights for line failure. This unit provides DTE interface. Functions (1) ISDN line Access • 2 ports of the primary tributary bit rate interface per panel are provided. • One port accommodates three channels. • D ch protocol conversion is executed in PIIFC. • T1 (private line) interface is available with the parameter setting. (2) Line Setting • The line setting per channel unit is possible. • Teleconference type can be selected with multipoint connection or point- to-point connection path. (3) Selection of Receive Clock • The receive clock from any connection port is selected with CPU control. The extracted clock signal is sent to PG/SIO unit. (4) Line Alarm Indication • The line alarm per channel is indicated. (5) Remote/Local loopback • Remote/Local loopback per port is performed with CPU control.
Page 32NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit 4.14 Fig. 4-6 shows block diagram of H0-INF unit. Figure 4-6: Block Diagram of H0-INF Unit PORT2 PORT1RELAY RELAYIPAT#2 IPAT#1AC FA # 2 AC FA # 1MTSC#4 MTSC#3 MTSC#2 MTSC#1 ICU DEBUG2 DEBUG1LED LED DIP SW DIP SWPIIFC #2 PIIFC #1CPU G/A ROM RAM HSCX CPU G/A ROM RAM HSCX DIP SW LED 44 4 44 4 4 4 4 4 H221 MUX LDRLDS LB CLOCK (4M, 8K) +5V CPU BUS INT (TS24) DCL (2M) DCL (2M) (TS24) 232C 232C DCL (2M)
NECA 340-414-100 Revision 2.0Page 33 MCU 5000A Multipoint Control Unit General Description Manual H0-INF Unit Interface (1) Table 4-6 shows the electrical specification. This interface conforms to ITU-TS G.703, I.431. (2) Table 4-7 and Fig. 4-7 shows H0-INF Connector Pin Assignment. Figure 4-7: H0-INF (CH1 to CH16) Connector Pin Assignment Table 4-6: Electrical Specification ITEM SPECIFICATION Transmission Rate 1.544 Mbps ±50 ppm (Data rate: 64 to 1536 kbps, 64k step) Line code AMI (B8ZS) Frame 12/24 Multiframe format Pulse amplitude 3.0 ± 0.7 V Spectrum half width 324 ± 38 nsec Impedance 100 _ balanced Equalizing distance 0 to 210 m 7 steps programmable setting Connector D-sub 15 pins female Table 4-7: H0-INF (CH1 to CH6) Signal Assignment PIN NO. SIGNAL NAMEI /O REMARKS PIN NO. SIGNAL NAME I /O REMARKS 1 SHIELD Cable shield 9T (B)+ OUT Transmitting Data (B) 2 T (A)- OUT Transmitting Data (A) 10- 3 - 11R (B)+ IN Receiving Data (B) 4 R (A)- IN Receiving Data (A) 12- 5 - 13- 6 - 14- 7 - 15- 8 SG Signal ground 81 9 15
Page 34NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit D: EC H211 MUX UnitGeneral 4.15 In EC H211 MUX unit, the received data signal from terminal CODEC via LIF unit is synchronized with H.221 or multiframe. This unit also demultiplexes the synchronized data signal to the audio coding data, video coding data, and MCU Control Data. This unit also multiplexes the sum-processed audio coding signal in A CODEC and A SUM units, converted video coding signal in V SW/LSD IF unit, and LSD, and sends the multiplexed data signal to LIF unit. In this time, The control data, alarm and bit error rate data are transferred between MCU 5000As via service channel with H.221 frame. 4.16 This unit is assigned one unit per one teleconference terminal in multipoint teleconference. Maximum 8 units can be mounted in a subrack. Functions • H.221 synchronizing detection or synchronizing phase adjustment. • Multiplexing and demultiplexing for the data signal in service channel. • Conversion to H.221 synchronous signal. • Alarm detection • Loopback test and Self-diagnosis
NECA 340-414-100 Revision 2.0Page 35 MCU 5000A Multipoint Control Unit General Description Manual 4.17 Fig. 4-8 shows block diagram of EC H221 MUX unit. Figure 4-8: Block Diagram of EC H221 MUX Unit LD1 IN LD2 IN LD3 IN LD4 IN LD1 OUT LD2 OUT LD3 OUT LD4 OUTDIST4-1 SEL TO /F RO M LIF (LD S/R)MTSC H221 SYNCHRONIZATION DETECTOR CPU CPU INFDELAY CONTDMUX PG MUX4-1 SEL DIST LD1 OUT LD2 OUT LD3 OUT LD4 OUT LD1 IN LD2 IN LD3 IN LD4 IN V SW/LSD A CODEC (MD-R) V SW/LSD (LSD) V SW/LSD A CODEC (MD-S) FROM PG/S IO TO M CONT
Page 36NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit E: V SW/LSD IF Unit General 4.18 The V SW/LSD IF unit switches the video signal between RD IN and SD OUT from EC H221 MUX unit. This unit receives the low-speed data demultiplexed from service channel in EC H221 MUX unit, and the proceed low- speed data is sent back to the EC H221 MUX unit. Functions (1) V SW This unit sends the video signal of the transmitting teleconference terminal received from the EC H221 MUX bus (MD-R) to EC H221 MUX bus (MD-S) of the receiving terminal. The video signal of maximum 8 points can be switched. (2) LSD IF Receiving/sending low-speed data within the data from service data. The monitoring function is provided. low-speed data with frame format of HDLC frame is sent/received from HDLC controller (HSCX). The data of the electrical whiteboard (option) and MCU control is sent/received through LSD between the terminal and MCU 5000A. (3) LED LEDs indicate the teleconference, originating, and operator terminal are provided. (4) PN Pattern Generator/Checker The test functions for this unit and other unit in the MCU 5000A are provided.
NECA 340-414-100 Revision 2.0Page 37 MCU 5000A Multipoint Control Unit General Description Manual 4.19 Fig. 4-9 shows the block diagram of V SW/LSD IF unit. Figure 4-9: Block Diagram of V SW/LSD IF Unit (1of 2) DBDIN OUT TSC48 4 4 MTSC MTSC DIN OUT TSC DETECTING ERROR TDBMDR MDS 8 4 4 8 8 8 8 8 8D HC151 Y S C B A Y G2 C B A Y G2 C B A TDH TEST VLB HC138 HC151 D W S C B A TSC 4MCK - 2MCK - 8 4 4MDS DQ HC273 TDS PN PAT T E R N CHECKER BURST CLK BURST CLK PN PAT T E R N CHECKERTSC TEST: TESTING CONTROL VLB: VIDEO LOOPBACK TSC: TBY STATE CONTROL TDR: PN PATTERN OUT
Page 38NECA 340-414-100 Revision 2.0 General Description Manual MCU 5000A Multipoint Control Unit Figure 4-9: Block Diagram of V SW/LSD IF Unit (2 of 2) R x D1 T x D1 T x CK1 R x D2 T x D2 T x CK2H S C X R x D1 T x D1 T x CK1 R x D2 T x D2 T x CK2H S C X R x D1 T x D1 T x CK1 R x D2 T x D2 T x CK2H S C X R x D1 T x D1 T x CK1 R x D2 T x D2 T x CK2H S C X D71054 DIST SEL LSD R IN LSD S OUT V11 CLK 2M CLK 4M CLK CN3LSD R0 LSD S0 LSD CK0 CPU BUS