GE Logiq 9 Service Manual

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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 7 Diagnostics/Troubleshooting 7-33
7-7-4-9 Diagnostic Utilities
This Diagnostic Group contains useful utilities, which provide either a diagnostic or calibration tool for 
the user.
•Acq HW Information Utility - Collects all available information about the Acquisition Hardware. 
This utility enumerates the Acquisition Hardware and writes a file containing all of the Vital Product 
Data (VPD) associated with each installed board.
•Transmit Utility - Start: Selectively fires each transmitter in the System with various parameters 
for testing purposes.
This utility exercises the transmitter of each channel, such that external test equipment can 
measure the generated waveforms. This tests the analog circuitry of the transmitter, as well as the 
digital generation of the transmit waveforms on the TDs.
•Transmit Utility - Change Channel
•Transmit Utility - Stop
•Receive Utility - Single Frame - Selectively activates each receiver in the System for testing 
purposes.
•Receive Utility - 8 Frames: This utility exercises the receiver of each channel, such that an external 
source may be used to test the receivers. The received waveform is fed through the Acquisition 
Hardware and retrieved from the Image Memory.
•Visual Channel Utility - The user can selectively turn ON/OFF transmitter and/or receiver 
channels. By viewing the image as this is done, the user may be able to identify bad channels.
NOTE: This Visual Channel Utility works only with the 10L probe.
• High Voltage Reset Utility
• Probe Select Utility 1-4
• Probe ID Read Utility
• Commutator State Write Utility - Diagnostic not yet implemented 
						

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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
7-34 Section 7-7 - Acquisition Diagnostics
7-7-4-10 Calibration Utilities
Touchscreen Calibration: Follow the directions on the Touchscreen. As each of the cross-hairs 
appear, touch them with your finger or a pencil eraser.  You MUST hold your finger on the cross-hair 
until it moves to the next location. If you just tap the calibration cross-hair, there is a better than average 
chance your calibration will be corrupt.
NOTE: Do NOT use sharp, pointed objects to press on the Touchscreen. You should also be careful if 
you have long,sharp finger nails. The Touchscreen can be damaged by sharp objects.
After all the cross-hairs are touched the screen is calibrated.
Start/Stop Touchscreen Verification: Select START TOUCHSCREEN VERIFICATION
 and 
EXECUTE
. The Start Touchscreen Verification brings up a grid.  Each time you touch the screen a small 
red dots appears.
To terminate the verification, select STOP TOUCHSCREEN VERIFICATION
 and EXECUTE.
Front-End Calibration Utility - DC Offset: All probes must be disconnected. Measures the DC offset 
of each channel and writes a calibration file for use in zeroing the offset. Application code may then 
utilize these values to zero each channels DC offset, by appropriately programming the Rigel beam 
forming ASICs on the TDs.Figure 7-36  Calibration Utilities
Click on the movie camera icon to view the video illustrating the calibration of 
the Touch Panel.
4 minutes and 47 seconds 
						

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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 7 Diagnostics/Troubleshooting 7-35
Section 7-8
Preferred Test Strategy for PCI 9054 Interface
NOTE: This only applies to systems with the SCB, EQ and BMP boards configuration. This does not 
apply to systems with EBM Boards.
Several LOGIQ™ 9 circuit boards utilize the PCI 9054 PCI Bus Master I/O Accelerator chip. This section 
defines a common testing strategy for a PCI interface implemented with the 9054. Deviation from this 
strategy may be required or preferable in some circumstances. When this is the case, the diagnostics 
SDD must note the deviation.
Depending upon where in the diagnostic an error is found, the nature of the error can be determined.   
The following are examples of messages that may be reported:
• Bad C/BE# Line (give number)
• Bad AD Line (give number)
• Bad Serial EEPROM
7-8-1 General Strategy
Some degree of functionality is already tested when the system boots up and enumerates the PCI bus. 
The idea here is to toggle all of the relevant PCI signals to determine if they are functioning (its possible 
that the PCI interface was detected and set up by the host, but only by luck due to some signal error). 
The focus is on the C/BE# signals and the AD lines. Also, we want to know that the serial EEPROM is 
communicating properly with the PCI 9054. For all practical purposes, the control lines on the PCI bus 
will need to be functioning properly for all of the data transfers to occur correctly.
While this testing strategy is complete in terms of the signal lines, there is no explicit validation that 
memory reads and writes will function properly, due, for instance, to some error in the PCI 9054 chip 
(all of the interface accesses occur through the VPD functionality, as described below). Any 9054 
memory access errors will be found during the boards memory test.
Also, this interface test does not test the DMA functionality on the 9054, since these DMA channels are 
not utilized by most 9054 implementations in LOGIQ™ 9. Any DMA functionality that is used will be 
tested via a board-level or system-level memory diagnostic (notably, TD Channel Memory transfers 
from the SCB).
Lastly, PCI timing issues (e.g. wait states, delayed reads, etc.) are not tested. It is assumed that any 
required timing functionality in the interface will be tested during the boards memory test.
7-8-1-1 Strategy for Testing the C/BE# Signals
By selectively asserting each of the byte enable bits for four successive reads, the validity of the C/BE# 
signals can be verified. This will suffice for testing the various commands that can be issued over the 
PCI bus. Testing the command modes explicitly would be significantly more difficult. Also, not all boards 
support all commands, and the pre-fetching modes are hard to verify before the on-board memory itself, 
is verified.
7-8-1-2 Strategy for Testing the AD Signals
Since the address and data are multiplexed on the PCI bus, we can utilize the data to validate the signal 
lines.
7-8-1-3 Strategy for Testing the EEPROM Link
The VPD function of the PCI 9054 allows the host to write and read from the serial EEPROM. An Lword 
location in the EEPROM is reserved for this purpose. 
						

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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
7-36 Section 7-8 - Preferred Test Strategy for PCI 9054 Interface
7-8-2 The PCI Interface Test Details
The following accesses to the VPD functionality must be performed with Configuration Reads/Writes.
Given the reserved diagnostic location in the VPD:
1.) Write the Lword 0x7856 3412 to the VPD location. 
2.) Next, read back the entire Lword, and note its value, even if its not what was written.
3.) Now, read back the data again, excluding the least significant byte, and ensure that the upper 
three bytes match the upper three bytes of the data read back in step 2.
4.) Repeat steps 1-3 three more times, each time changing the excluded byte location.
5.) Finally, utilizing multiple writes and reads, walk ones and zeros up the AD lines (same address, 
different data) to ensure that they are functioning.
Steps 1-4 will verify the C/BE# signal lines, even if the data read back is corrupt. Note that if the data is 
too corrupt (the read in step 2 cant distinguish the bytes) then the test must fail. Otherwise, as long as 
the byte reads match the corresponding bytes of the Lword read, the C/BE# signal lines are verified.
NOTE: If all of the reads performed here result in all 0s being read, there is likely a problem with the EEPROM, 
not the PCI bus, itself. This should be reported to the user.
7-8-3 Verifying the PCI Interface Test
The following steps are suggested as a means of verifying a PCI Interface diagnostic that utilizes this 
strategy:
• Check the C/BE# lines with a logic analyzer, to ensure that the byte-wide accesses are individually 
asserting each of these signals.
• Corrupt the C/BE# lines and verify failure.
• Corrupt the AD lines and verify failure.
• Corrupt various pins on the EEPROM and verify failure.
NOTICEThe byte-wide access must not be implemented with an Lword access followed by a masking operation 
on the host. This type of byte-wide access wont test the C/BE# signal lines. 
						

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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 7 Diagnostics/Troubleshooting 7-37
Section 7-9
Preferred Test Strategy for Memory
It is desirable to have a uniform memory testing strategy across the entire platform. This section defines 
a common testing strategy for on-board memory. Deviation from this strategy may be required or 
preferable in some circumstances. When this is the case, the diagnostics SDD must note the deviation.
The three things that require testing for any memory are:
• The address bits
• The data bits
• The internal memory cells
As with all diagnostics, execution time is an important consideration. This strategy has been developed 
with that in mind.
Note that this procedure holds for registers, also. In that case however, testing the address bits is 
irrelevant. Also, for registers, we additionally need to test for floating pins.
Depending upon where in the diagnostic an error is found, the nature of the error can be determined.   
The following are examples of messages that can be reported:
• Bad Address Bit (give number)
• Bad Data Bit (give number)
• Bad Memory Cell (give address and bit)
• Floating Pin (give register address and bit)
Also, a log file consisting of memory addresses, expected data values, actual data values and bit-wise 
differences should be provided. For example, a line in the log file might look like this:
7-9-1 General Strategy
This strategy is intended to fully test the address and data lines of a memory device and satisfactorily 
test the devices internal memory cells, while minimizing the number of read and write cycles required.
7-9-1-1 Strategy for Testing the Address Bits
Consider the address memory locations defined by having a single 1 or a single 0 in the address, as 
seen by the memory device. Write a unique data value to each of these addresses, and then read and 
verify the data. Next, write the bit-wise inverse of the same data to the same locations, and then read 
and verify the inverted data. At this point, the address lines of the memory are fully tested.
7-9-1-2 Strategy for Testing the Data Bits
To fully test the memorys data bits, start at the base address and write all of the data words defined by 
having a single 1 or single 0 to the memory. Read and verify the data.
NOTE: The designer can combine some or all of the data testing within the address testing.
Address OffsetExpected DataActual DataDifference Mask
56 (0x38)0x38 (0011 1000b)0x2A (0010 1010b)0x12 (0001 0010b) 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
7-38 Section 7-9 - Preferred Test Strategy for Memory
7-9-1-3 Strategy for Testing the Internal Memory Cells
To test the internal memory cells, start at the base address and fill the memory with an alternating 
pattern of:
0x55555555
0xAAAAAAAA
0x55555555
...
(masked appropriately)
Read and verify the data. Repeat this, filling the memory with an alternating pattern of:
0xAAAAAAAA
0x55555555
0xAAAAAAAA
…
(masked appropriately)
Read and verify the data.
This test for the memory cells is not exhaustive. However, it does ensure that adjacent cells are not 
stuck together and that each cell can take on a 1 or a 0 value.
7-9-1-4 Strategy for Testing for Floating Pins (Registers Only)
Anytime a write-then-read operation is performed on a memory location, such as a register, it is possible 
for certain faults (e.g. disconnected pins) to go undetected. This is due to the time it takes for a data line 
to settle to its default value (through a pull-up resistor). If the write-then-read turnaround time is fast 
enough, and a register pin is not connected to the data line on the circuit board, then the read operation 
will only reflect the un-relaxed data line, instead of the registers memory cell at that bit.
To uncover a floating pin fault, perform the following steps:
• Write all zeros to the register - 0x0000 0000 with no mask.
• Next, write all ones to a different register on the same data bus - 0xFFFF FFFF (again, no mask).
• Read the first register, apply the data mask, and verify that the data is all zeros. Any 1s in the read 
data imply a floating pin at that bit. 
						

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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 7 Diagnostics/Troubleshooting 7-39
7-9-1-5 Strategy for Testing Multiple-Part RAMs
Special consideration must be paid to the data patterns written to a RAM that is implemented with more 
than one parts. For example, consider a 32-bit wide RAM that is implemented with 8 4-bit wide parts. 
For this RAM, the test data pattern width must be considered to be 4 bits wide and repeated on all eight 
nibbles of the 32-bit Lword. For example, if we wanted to write 0x3 to test the data bits, we should write 
0x33333333, such that each of the eight nibble-wide parts have the test data applied. Thus, the 
maximum one-hot (one 1, all the rest 0) data value we would ever write to the local memory is 0x8, 
which would be applied to the RAM as 0x88888888.
When implementing the Preferred Strategy for Testing Memory for a multiple-part RAM, simply consider 
the data width to be as wide as a single part, repeating the data to fill the 32-bit Lword. The procedure 
then still holds.
Additionally, this test must ensure that the individual RAM devices are all being accessed. To that end, 
unique data must be written to each part. Thus, (continuing with the 8, 4-bit wide RAM example) we 
have the additional need to apply test data such as 0x00000008, x00000090, 0x00000A00, 
0x0000B000, 0x000C0000, 0x00D00000, 0x0E000000, and 0xF0000000 to eight different local RAM 
addresses. When this data is read back and verified, we know that the data lines are not crossed or 
corrupted.
The reasoning behind all of this is that if the data is incrementing from a small value, for instance, then 
all zero data will be written to and read from devices that comprise the most significant data in the RAM 
bank. Therefore, we cant be sure that these devices are being addressed properly (assuming the non-
targeted locations contain zeros too). Utilizing the bitwise inverse of the data in the address test 
somewhat alleviates this problem; however, there is little overhead associated with the extra accesses 
to ensure that individual RAM devices are all being accessed properly. 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
7-40 Section 7-10 - I/O Devices
Section 7-10
I/O Devices
7-10-1 OP Panel Utilities - OP Panel Interface
Front Panel key functionality can be tested using a program (ScFpApiTest) currently accessed through 
Service Diagnostic User Interface or by running the program located on the “C” drive of the Back End 
Processor.
7-10-2 Launching the Program without the Global Service User Interface
1.) The Ultrasound Scanner should be turned off.
2.) Install the service key in the USB port on the External I/O.
3.) Power up the Ultrasound Scanner.
4.) At the first popup window select MAINTENANCE MODE
.
5.) Enter the current service password.
6.) Select the EXIT TO WINDOWS
 option.
7.) In Windows select START
 > RUN
8.) Type in: C:\Musashi	arget\bin\ScFpApiTest.exe.
9.) Click on OK
.
10.) Click on VERSION
. If there is communication with the keyboard there will be a readout of the 
software version In the Log areaFigure 7-37  ScFpApiTest Screen 
						

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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 7 Diagnostics/Troubleshooting 7-41
7-10-3 Testing the Front Panel Keys
With the ScFpApiTest active, push a button on the keyboard. A readout of the button id number and the 
indication that it was pushed and released (1 and 0) will appear in the Log area as shown in Figure 7-38.
The button id list is not available. The id number of the button is not important. What is important is the 
fact that a 1 and 0 are returned indicating the button push and release.
Test encoders by rotating them and getting relative values as indicated in Figure 7-39.
The important thing is the return of a 1 and 0 as the encoder is rotated.Figure 7-38  Button Push Result
Figure 7-39  Encoder Rotation Results 
						

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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
7-42 Section 7-10 - I/O Devices
Test slide pots (TGC) by moving them through their range. Feedback will be returned to the Log area 
as shown in Figure 7-40.
The important thing to watch here is the slide pot number that is moving and ensure that it’s value 
changes. In Figure 7-40 slide pot s0 is changing.
NOTE: It is important to remember that the trackball and alpha-numeric keyboard are not tested by this 
program. Moving the cursor in Windows with trackball would indicate its functionality. PC 
Diagnostics in the Common Service Interface will check the alpha-numeric keyboard.Figure 7-40  Slide Pot Test Results