GE Logiq 9 Service Manual

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-1
Chapter 5
Components and Functions (Theory)
Section 5-1
Overview
5-1-1 Purpose of Chapter 5
This chapter explains LOGIQ™ 9’s system concepts, component arrangement, and subsystem 
function. It also describes the Power Distribution System (PDS) and probes.
 
Table 5-1 Contents in Chapter 5
SectionDescriptionPage Number
5-1
Overview5-1
5-2
General Information5-2
5-3
Front End Processor5-5
5-4Back End Processor (BEP)5-23
5-6Patient I/O (Currently not supported by the LOGIQ™ 9)5-36
5-7Internal I/O5-37
5-8
Top Console5-45
5-9
Monitor5-46
5-10
External I/O5-46
5-11Peripherals5-49
5-12Modem5-50
5-13Power Distribution5-52
5-14
Mechanical Descriptions5-57
5-15
Air Flow Control5-59
5-16
Service Platform5-59 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-2 Section 5-2 - General Information
Section 5-2
General Information
LOGIQ™ 9 is a phased and linear array ultrasound imaging scanner. It has provisions for analog input 
sources like ECG and Phono. A Doppler probe may also be connected and used. 
The system can be used for: 
- 2D Gray Scale and 2D Color Flow Imaging 
- M-Mode Gray Scale Imaging 
- Color M-Mode 
- Doppler
- Different combinations of the above modes
LOGIQ™ 9 is a digital beamforming system.
Signal flow travels from the Probe Connector Panel to the Front End Electronics, to the Back-End 
Processor, and finally displayed on the monitor and peripherals.
System configuration is stored on the hard drive and all necessary software is loaded from the hard 
drive on power up.
Figure 5-1   LOGIQ™ 9 Major Components
Front Bumper
Backend Processor Chassis
CD-ROM
3.5” MOD
ECG Module
B/W Printer
Operator Console
Gel Warmer
Monitor Controls
Name Plate
Monitor
Op. Panel Upper Bezel
Touchscreen/Display
TGC Slidepot Knobs
Front Cover
VCR
Probe Connector
Swivel Lock &
Brake Release
Brake & Swivel Release 
						

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-3
5-2-1 Block Diagram
Figure 5-2   LOGIQ™ 9 Simple Block Diagram
FRONT END PROCESSOR
PROBES
FRONTPLANE
FRONT END BACKPLANE DOPPLER
ATX POWER SUPPLYUPS
AC POWER
OP I/O PA N EL17 Monitor
USER INTERFACE
SONY COLOR PRINTERUP-2900MDPC2IO
PCVIC
PC MOTHERBOARD
POWER ON/OFF (RESET*)
FLOCK
OF
BIRDS
(optional)Ethernet
PC2IP SOUND
CARD PCI
VIDEO AGP
VIDEO
XDI
FR
F
AMP
TD3
TD4
TD5TD6
TD7 TD0
TD1
TD2
F
E
PSSC
B EQ4BMP
EXTERNAL I/O
MODEMAC CONTROLLER
XFMR BOX
TO MONITOR
TO PC
TO PERIPHERIALSTO MODEM
TO CARD RACK
230Vac230Vac
11 5 Va c
115 or 230Vac
2
30
V
a
c1
15V
a
c
BACK END PROCESSOR
ECG Patient Interface
3.5 MOD
CD-ROM
Hard Drive
SONY VCRSVO-9500MD
SONY B/W PRINTERUP-890MD
TO OUTLET
INTERNAL I/O
PCI   CABLE
230Vac
Vid
eo Outp
uts
Netwo
rk Co
n
nection
USB
 Connectio
n 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-4 Section 5-2 - General Information
5-2-2 Dataflow Control Description
5-2-2-1 Data Sets
Each scan mode will produce data to a corresponding data set in the Image Memory. The data sets are 
represented in ring-buffers. Each active data set will be allocated to one of the following types of 
acquisition data:
• 2-D tissue data
• Doppler data
• M-mode data
• 2-D Color flow 
• Trace data
• Video Y-component data
• Video UV-component data
• Color M-mode data
•RF data 
						

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-5
Section 5-3
Front End Processor
The Front End Processor generates the strong bursts transmitted by the probes as ultrasound into the 
body. It also receives weak ultrasound echoes from blood cells and body structure, amplifies these 
signals and converts them to a digital signal.
5-3-1 Front End Processor Power Supply Board (FEPS, FEPS2, FEPS2.1)
The power supply assembly receives approximately 220VAC from the secondary side of  the mains 
isolation transformer.
The FEPS assembly supplies DC regulated power to the Front End card rack of the LOGIQ™ 9.   The 
assembly is configured as a PCB which fits into the right-most slot of the Front End card rack. It 
interfaces with the back plane to supply power to the Front End circuit boards.
A general enable signal (PS_ON) controls enabling and disabling all FEPS Low Voltage outputs. These 
include +5VA, -5VA, +5V, 3V3, +12V, and +15V (all except PHVP ‘High Voltage’). An Enable circuit on 
the FEPS detects when PS_ON becomes valid and holds all outputs off until then. Figure 5-3   The Front End
XDIFTD
Board
Sum
Rigel
EqualizationBarrel Shift
Digital GainNCOFIR
TGC Gen
XDIF
Control
Commutator
Control
Temperature
SensorsPower
Supply
Monitors
Scan Bus
Interface
B Mode ProcessorSynthetic
ApertureAxial Interp
DetectorVector
CompoundSmoothing
Filter
Rate
ConverterDynamic
Range
Edge
EnhanceFocal
Zone
SplicerB Mode
M Mode
Output
M Peak
Hold
Scan Bus
Interface
TD
Control
Bus40P0
40P1
TxSync
BPCLK
HV
Pwr Sup
ControlI,Q
Grey 2D, M
PCI Cable to BEP
Scan Control Board
Scan
Sequencer
TD ControlTxSync
RxSync
GeneratorSystem
Clock
Generator/
Distributor
PCI-PCI
Bridge
Ring Buffer
I,Q
Capture
Processed
Capture
(B, M)
PCI Bus
Scan Bus
T/R SwitchProbe
Port
MUXA/D
Pulser
RFAmpPreAmp TGC
Video
Capture
Top Plane
Front End
Power Supply
240
VAC
+5 V +3.3 V
+5 V analog
-5 V analog
PS ON
Internal I/O
+12 V
+120 V
I,Q
I2C Master
Scan Bus
PCI Bus 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-6 Section 5-3 - Front End Processor
5-3-1Front End Processor Power Supply Board (FEPS, FEPS2, FEPS2.1) (cont’d)
The high voltage lockout circuit monitors the +5VA, -5VA, +12VA and 3V3 supplies and locks out the 
PHVP supply in the event that any one of them go below 10% of their nominal value.
PWR_OK is an active high TTL compatible output which provides a status indication of the AC input 
power. It should be capable of sinking 5mA maximum. The signal switches to a TTL ‘High’ when the AC 
input voltage reaches the minimum specified input level at power up. Upon loss of input voltage, 
PWR_OK will go ‘Low’. 
5-3-1-1 FEPS3
The FEPS3 Board was introduced with R3.0.0 Software and BT’03. It is not backward compatible with 
prior hardware as it provides the new voltages (+/- 6V and 13V) required by the TD5s and RFAMP2. 
5-3-2 Front End Subsystem
The LOGIQ™ 9 Front End Subsystem consists the XDIF (Transducer Interface) board, RF Amp board 
and eight TD (Transmit Delay) boards.
The Front End Subsystem provides 128 receive and 128 transmit channels as well as gain and 
bandpass filtering of the received signal. Table 5-2    FEPS, Output Comparison
System Name
FEPS, FEPS2, FEPS2.1
Nominal OutputFEPS3 
Nominal Output
5VPA +5.05V+6.0V
5VNA -5.05V-6.0V
5VP +5.05V +5.05V
3V33.33V3.33V
PHVP+121.2V / +24.2+121.2V / +24.24V
12VP12.1213.0V
15VP +15.15 +15.15
Figure 5-4  Basic Front End SubSystem 
						

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-7
5-3-2-1 XDIF (Transducer Interface) Board
The XDIF supports four 128 Channel probe ports with the ability to select one of the four probe ports. 
The XDIF supports a probe multiplexer requiring a 200V (+100V and -100V). The multiplexer in the 
probe will select 128 of the out of up to 192 channels.
The XDIF uses a T/R (Transmit/Receive) switch on each output to the RF Amplifier board. During 
transmit the T/R switch prevents the high voltage transmit pulser from damaging the receive 
preamplifier. During receive the T/R switch isolates the receive preamp from the transmit high voltage 
pulser.
5-3-2-2 Top Plane
Connects the receive signals from the XDIF board to the RF Amplifier board at the front of the circuit 
boards.Figure 5-5  XDIF Board Functions 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-8 Section 5-3 - Front End Processor
5-3-2-3 RF Amp, RF Amp1.2, RF Amp2 Board (Radio Frequency Amplifier Board
The RF Amplifier board shall contain 128 channels of the circuitry that is necessary to amplify the small 
electronic echo signals that are received from the probe transducers. Each channel shall consist of a 
low-noise, active input termination preamplifier, a time-gain compensation (TGC) amplifier, and a low 
noise differential drive amplifier (buffer). The RF Amp board shall physically reside in the Beamformer 
card cage adjacent to the XDIFF board.
The probe level analog input signals shall enter the RF Amp board on a series of board to board 
connectors that mate the RF Amplifier Board to the XDIFF Board. These connectors carry the 
transducer level receive signals that originate at the probe and make their way through the probe 
interface relays, and T/R switches. The digital interface, power supplies, and reference ground shall be 
provided to the RF Amp board by the system backplane.
Each amplified signal generated by the RF Amp board shall provide a differential output and drive filter 
circuitry located on the TD boards via the system backplane. The TD boards perform an anti-alias 
filtering operation and convert the transducer signals to a 12 bit data stream that feeds the digital 
beamforming electronics.
RF Amp2 Board
The RF Amp2 Board was introduced with R3.0.0 Software and BT’03. It is not backward compatible with 
prior hardware as it requires the new voltages (+/- 6V and 13V) provided by the FEPS3 Board. Figure 5-6  RF Amp, RF Amp2 Functions
Figure 5-7  RF Amp Board Functional Block Diagram 
						

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-9
5-3-2-4 TD, TD4, TD5 (Time Delay) Boards (8)
Major functions of the TD boards are:
- Transmitter
- Analog Receive
- A/D (Analog to Digital conversion)
- Digital Receiver (Rigel Beamformer Chip)
- Control & Timing
The TD (Time Delay) boards send 128 transmit signals to the XDIF board. The 128 receive channels 
from the RF board get low pas filtered, converted from analog to digital and then use the Rigel 
beamformer chip to generate complex digital data signals representing one or two beams of ultrasound 
echo information sent to the EQ board.Figure 5-8  Basic TD Board Functions
Figure 5-9  Basic TD Input/Output Signals 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
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IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-10 Section 5-3 - Front End Processor
5-3-2-4TD, TD4, TD5 (Time Delay) Boards (8) (cont’d)
Major control siganal from the EQ board are the Digital TGC/VREF and Serial Control Bus (I
2C). Control 
signal between the Scan Control board consist of Power, Timing Clocks, TD Control Bus and Fault 
Interrupts
Time Delay (TD, TD4, TD5) Board Function Summary:
• Each board assigned to a subset of 16 channels.
• Generates and amplifies the excitation waveform for each channel.
• Digitizes the input RF signal from the RF Amplifier board.
• Applies dynamic apodization, dynamic receive delays, and filters to the digitized RF signal.
• Automatically adapts receive beams for speed or resolution depending on scans.
• Sums detected echo channel to channel, then board to board. (Boards must be contiguous.) The 
last TD forwards the total output to the EQ.
• Monitors current consumed for transmit and issues a fault signal if overcurrent is detected.
TD5 (Time Delay 5)
The TD5 Board was introduced with R3.0.0 Software and BT’03. It is not backward compatible with prior 
hardware as it requires the new voltages (+/- 6V and 13V) provided by the FEPS3 Board. Figure 5-10  Basic TD Input/Output Control Signals