GE Logiq 9 Service Manual

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-21
5-3-6EBM, EBM2 Board (cont’d)
5-3-6-3 EBM/EBM2 Interface with XDIF relay board
The EBM/EBM2 EQ section supports an eight-bit read/write data interface to the XDIF relay board. The 
interface is used to transfer commutator control information to the selected probe and provides host 
access to the XDIF relay board itself. The EBM/EBM2 board monitors four probes present and four 
probe hook lines from the XDIF relay board. The EBM/EBM2 EQ section monitors the lines, and 
generates an interrupt signal when any of the signals change state. The interrupt signal will be 
debounced to limit the frequency with which probe interrupts may be generated. The EBM/EBM2 board 
also measures the temperature of the selected probe over two lines from the XDIF relay board. The 
SCE pulse signal connected to the EBM/EBM2 EQ section in order to be able to support the Global 
Beamforming future development.Figure 5-17  EBM/EBM2 Board Block Diagram
Power Supply 
HV Control
Probe 
Temperature 
Sensor
High Speed
SSRAM 
~ 9Mbit
Fan Control /
Power Supply
Measurement
Configuration 
Flash
(Host Programmed)
Barrel
Shifter
Delay
Multiplier
NCOLUT
17 I(L,R)
17 Q(L,R)16 Q(L,R)
Complex
Mult
32-tap
FIR
32-tap
FIR16 I(L,R)
16 Q(L,R)
Barrel
Shift &
Output 
Block16 I(L,R)
16 Q(L,R)
Coef
RAM
Coef
RAM
24I(L,R) TD: I-Data
24Q(L,R) TD: Q-Data
CLK-10MHz
CLK-40MHz
16
5
Analog 
DelayBase
TGCAnalog 
TGCV-ref
GEN
Dynamic
Apodization
Digital 
TGC
MUX
SCAN
Ctrl
I/FPCI
I/FI2C
I/FXDIF/
Probe
I/F
16 Q(L,R)
16 I(L,R) TGC / Vref Bus
Commutator
Ctrl
I/F
Gain Mod’s
5
PS
Ctrl
I/F
Test
Vector
GeneratorSynthetic
ApertureAxial
InterpolationLow
Pass
FilterDetector &
Vector
Compound16
16
16
16
16
1615Rate
Converter15
Vector
Configuration
Dynamic
Range
CompressEdge
EnhanceSplicer88
B-Mode
Output
M-Mode
Output
8
8
15
8
8
B/M Mode
Output
Test Vector
Capture
10 MSB
PCI
I/F
Local SCAN Bus
FIFO
8Kx18
FIFO
8Kx18
FIFO
8Kx18
SRAM
64Kx16
PCI BUS
SCAN CONTROL BUS I2C BUS
CL K-20MH z
CLK-20MHz
IQ (Q) Data
(I) Data XDIF Interface Bus XDIF Probe Interface BusPower Supply Control
16
RXSYNC
TXSYNC
TXSYNC
RXSYNC Delayed
RXSYNC Delayed
16 HV Line
16 I(L,R)
5TFC
Power Supply 
HV ControlPower Supply 
HV Control
Probe 
Temperature 
SensorProbe 
Temperature 
Sensor
High Speed
SSRAM 
~ 9MbitHigh Speed
SSRAM 
~ 9Mbit
Fan Control /
Power Supply
MeasurementFan Control /
Power Supply
Measurement
Configuration 
Flash
(Host Programmed)Configuration 
Flash
(Host Programmed)
Barrel
Shifter
Delay
Barrel
Shifter
Delay
MultiplierMultiplier
NCONCOLUT
17 I(L,R)
17 Q(L,R)
17 I(L,R)17 I(L,R)
17 Q(L,R)17 Q(L,R)16 Q(L,R)16 Q(L,R)
Complex
MultComplex
Mult
32-tap
FIR
32-tap
FIR
32-tap
FIR
32-tap
FIR16 I(L,R)
16 Q(L,R)16 Q(L,R)
Barrel
Shift &
Output 
BlockBarrel
Shift &
Output 
Block16 I(L,R)16 I(L,R)
16 Q(L,R)16 Q(L,R)
Coef
RAMCoef
RAM
Coef
RAMCoef
RAM
24I(L,R) TD: I-Data
24Q(L,R) TD: Q-Data
CLK-10MHz
CLK-40MHz
16
5
Analog 
DelayAnalog 
DelayBase
TGCBase
TGCAnalog 
TGCAnalog 
TGCV-ref
GENV-ref
GEN
Dynamic
ApodizationDynamic
Apodization
Digital 
TGCDigital 
TGC
MUXMUX
SCAN
Ctrl
I/FSCAN
Ctrl
I/FPCI
I/FPCI
I/FI2C
I/FI2C
I/FXDIF/
Probe
I/FXDIF/
Probe
I/F
16 Q(L,R)
16 I(L,R) TGC / Vref Bus
Commutator
Ctrl
I/FCommutator
Ctrl
I/F
Gain Mod’s
5
PS
Ctrl
I/FPS
Ctrl
I/F
Test
Vector
GeneratorTest
Vector
GeneratorSynthetic
ApertureSynthetic
ApertureAxial
InterpolationAxial
InterpolationLow
Pass
FilterLow
Pass
FilterDetector &
Vector
CompoundDetector &
Vector
Compound16
16
1616
1616
16
16
1616
1616
16
16
1616
16161515Rate
ConverterRate
Converter1515
Vector
ConfigurationVector
Configuration
Dynamic
Range
CompressDynamic
Range
CompressEdge
EnhanceEdge
EnhanceSplicerSplicer8888
B-Mode
OutputB-Mode
Output
M-Mode
OutputM-Mode
Output
88
88
1515
88
88
B/M Mode
Output
Test Vector
CaptureB/M Mode
Output
Test Vector
Capture
10 MSB
PCI
I/FPCI
I/F
Local SCAN Bus
FIFO
8Kx18FIFO
8Kx18
FIFO
8Kx18FIFO
8Kx18
FIFO
8Kx18FIFO
8Kx18
SRAM
64Kx16SRAM
64Kx16
PCI BUS
SCAN CONTROL BUS I2C BUS
CL K-20MH z
CLK-20MHz
IQ (Q) Data
(I) Data XDIF Interface Bus XDIF Probe Interface BusPower Supply Control
16
RXSYNC
TXSYNC
TXSYNC
RXSYNC Delayed
RXSYNC Delayed
16 HV Line
16 I(L,R)16 I(L,R)
5TFC 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-22 Section 5-3 - Front End Processor
5-3-6EBM, EBM2 Board (cont’d)
5-3-6-4 B–Mode Output Blocks
The B–mode output block collect vector data and tags for delivery to the Scan Control Board. It can form 
output vectors from one or multiple input vectors (multi–transmit focus). The vector tags are used to 
form the control bytes in the output vector. Only complete vectors are sent to the BM_OUTPUT Block. 
The maximum vector length shall be 512 pixels.
5-3-6-5 M–Mode Output Block
M–mode acquisition is nearly always a multiple firings per output vector operation. When the vector rate 
is higher than the display rate a peak accumulate function shall be used to provide an output which is 
the point–by–point peak signal amplitude of all the firings since the last output. The M–mode output 
block usually outputs one processed M vector after combining the receive vectors from several firings. 
The maximum ratio of input vectors to output vectors is 256, although this number is transparent to the 
hardware. M_GATE tag shall control when the current peak accumulation stops, the vector is sent and 
a new vector is formed. The peak accumulation shall be reset after the data is sent to the BM_OUTPUT 
Block. 
						

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-23
Section 5-4
Back End Processor (BEP)
The Back End Processor (BEP) receives the data from the Front End Electronics, stores it in memory, 
performs scan conversion to pixel domain, and drives the system RGB monitor.
Back End Processor software is also providing Color Flow, Doppler, and M-Mode Processing.
NOTE: Specifications mentioned about the Back End Processor (BEP) will be minimum requirements. 
The actual hardware could exceed these specifications as technology advances.Figure 5-18   CPU/Back End Processor BEP1
SOUND CARD
SLOT 5
DIGITAL OUTSPEAKER OUTMIC INLINE OUTLINE IN
PCI VIDEO
SLOT 3
AGP VIDEO
SLOT 2
SLOT 7
10/100bT
PARALLEL
COM1
COM2 (EXT)USB1
USB2
PC MOTHERBOARD
PCIO MODULEATX POWER SUPPLY
UPS
HARD DRIVE
ECG
MOD
CD RW
IDE #2
JWR1
SLOT 4
PC2IP RS232 #3
RS232 #4
I2C
PC2IP
SLOT 6
AC POWER
RS422
RGB  OUT
JFP1
SVGA OUT 1SVGA OUT 2 S/C VIDEO OUT
SVGA INPOWER
PCI BIRD CARD
Front Panel
ETHERNET
PCIO Board
PCVIC Board
HD LED
IDE #1
UPS Battery
Optional 3D
system
SLOT 1
Control
MIDDLE DRIVE BAY
BOTTOM DRIVE BAY
INTERNAL DRIVE BAY
TOP DRIVE BAY
CPU #1
CPU #2
256 MB DIMM
256 MB DIMMDIMM Slot #1DIMM Slot #2 DIMM Slot #3 DIMM Slot #4JWOL1
AGP Slot
PCI Slot #1
PCI Slot #2
PCI Slot #3
PCI Slot #4
PCI Slot #5 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-24 Section 5-4 - Back End Processor (BEP)
5-4-1 Enclosure
The EMC enclosure shall house an ATX Power Supply with UPS battery backup, an ATX style 
motherboard with minimum of 512 MB of ram and two 733MHz processors
5-4-2 PCI Cards
5 PCI slots on the mother board shall contain the following:
1.) PCI Video Card - Digital Video to the Touch Panel
2.) Sound Card - Sound Blaster Live for audio to speakers
3.) Blank or PCI Bird 3D Card - Option
4.) PC2IP Card - GE designed. PCI Bus interface to the Front End Processor
5.) Network Interface Card - 3Com Ethernet Card
5-4-3 AGP Video Card - SVGA Video to the PCVIC Card
• Analog output shall comply with the SVGA specification.
• Resolution shall be 800x600.
• Support for 32 bit True Color
• Minimum of 8 Mbytes of high speed Video RAM, expandable to at least 16 Mbytes.
• 128-bit internal memory interface.
• Hardware supported asynchronous bit block transfer (80 Mpixels/sec).
• Full Direct 3D and Open-GI support (desirable).
5-4-4 PCIO Board:
This GE designed board does not plug into any slot but is mounted to the inside of the PC chassis.
- Power and Internal PCI control signals
5-4-5 PCVIC Card
- Input from AGP Video card (BEP1.0) or Motherboard AGP Video (BEP 2.0)
This GE designed board does not plug into any slot but is mounted to the inside of the PC chassis.
- SVGA output to the image monitor
- RGB output to color printer
5-4-6 DGVIC, DGIO and ADD Cards BEP 2.1 (BT’02, November 2002)
The ADD Card is a PCI card that mimics the AGP video and provides a digital video output to the DGVIC 
board.
The DGVIC converts the digital video to RGBS, SVGA (to Monitor and External I/O), S-video and 
Composite video outputs.
The DGIO provides signals and power to I/O boards. Signals like PS_ON, I
2C, RS232, PC Power and 
PC On/Off. 
						

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-25
5-4-7 Additional Memory (RAM)(BT’03, October 2003) - BEP2.2
Additional memory was added to the motherboard for R3.0.0 Software and BT’03. one of the 256 MByte 
SIMM modules was replaced with a 512 MByte module. This brings the total RAM memory to 
768MBytes and designated the unit to be a BEP2.2.
5-4-8 DGVIC/DGIO Upgrade
It is possible that older P3 Back End Processor video chains could be upgraded to digital. This involves 
replacing the Analog AGP Video card with a Matrox video card that has analog and video outputs.
The PC2IO/PCVIC Tray assembly is also replaced with the DGIO/DGVIC Tray. 
Digital video is supplied by the Matrox video card to the DGVIC for distribution to peripherals. Monitor 
video is taken directly from the Analog output of the Matrox video card instead of the DGVIC.
5-4-9 UPS Battery Operation
The UPS batteries provide power to the Back End Processor to enable a controlled shut down of the 
processor. The UPS batteries will drain slightly when the system is in the off condition. The off condition 
is defined as:
- Circuit Breaker in the OFF position
- System unplugged from the wall outlet
If the system is left in the OFF condition for an extended period of time (3 to 5 days or more), the system 
may not boot up or may beep when turned ON. Should this occur, the system needs to recharge the 
UPS batteries. This could take 15 minutes to as long as 24 hours, depending on the battery age, system 
input voltage and system temperature.
To eliminate draining the UPS batteries, the system should remain plugged into the wall outlet with the 
circuit breaker in the ON position.
The expected life of the battery is approximately three (3) years. 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-26 Section 5-4 - Back End Processor (BEP)
5-4-10Internal Storage Devices:
• A 20 or 40 Gigabyte EIDE Hard Disk Drive (HDD) inside the Back End Processor cabinet.
• 3.5 inch Magneto-Optical Drive (MOD) (available from front of scanner).
• CD-RW Drive (available from front of scanner).
5-4-11 Location of the Back End Processor
5-4-12 Inputs
5-4-12-1 AC Power
 
5-4-12-2 DC Voltages
 
Figure 5-19   Backend Processor mounted in scanner
Table 5-5    AC Power
InputDescriptionConnection from:
230 VAC AC Power AC Distribution Box > Backend 
Processor
Table 5-6    DC Input Voltages 
InputDescriptionConnected to:
+5Vstb Standby voltage DC Power Supply via Backplane
GND Electrical GroundDC Power Supply via Backplane and II/
O
P3 Backend Processor
Front of 
ScannerLeft Sideof 
Scanner
P4 Backend Processors 
typically have a fan in the 
center of the cover 
						

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-27
5-4-12Inputs (cont’d)
5-4-12-3 Input Signals
5-4-12-4 Bi-directional Signals
NOTE: BEP2.x processors have one Com Port and six USB Ports. The Com Port is connected to the 
modem via the Internal I/O. A USB to Serial Converter feeds the external serial connection via 
the Internal I/O. BEP 2.1 Processors have digital video coming from a Matrox or ADD card 
going to the DGIO/DGVIC Tray. BEP 2.x processors have Ethernet and Analog Video on the 
motherboard. Table 5-7    Input Signals 
Signal NameDescriptionSignal Path 
PWR_OK* Power verification signal from Card Rack Card Rack > IIO > PC2IO 
ON/OFF SwitchSignal from the ON/OFF switch on the Control Panel and 
from the Reset button on the rear of the External I/O.Top Console > IIO > PC2IO
ON/OFF Reset (EIO) > IIO > PC2IO
I2C Register 
InterruptInterrupt signal from I2C Bus  EIO > IIO > PC2IO
Microphone in to 
BEPMicrophone signal from Monitor (Top Console)Top Console > IIO > BEP
Audio in to BEPAudio from VCR or Doppler Audio
Replay Audio from VCR > IIO > BEP
Doppler Audio Out from Card Rack > IIO 
> BEP
Table 5-8    Bi-directional Signals 
Signal NameDescriptionSignal Path 
UPS Control 
RS232Control Signals to and from the UPS BEP > IIO
RS232 XDCTRL Not Used  PC2IO > IIO > Not Used
I2C BusData bus used for Remote Control of External Units and for 
reading module versions.PC2IO > IIO > EIO
Spare RS232Not UsedPC2IO > IIO > Not Used
VCR Remote Ctrl 
(RS232)Control signal to Internal VCRPC2IO > IIO > VCR
USB #1USB bus to Top ConsolePC2IO > IIO > Top Console
COM 1 Can be configured to transfer report page data PC2IO > IIO > EIO
COM 2 ModemPC2IO > IIO > EIO (Rear of Module) > 
Modem
Ethernet Standard TCP/IP Ethernet BEP > IIO > EIO > External Network
USB #2USB Bus for External UnitsBEP > IIO > EIO > External USB Unit 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-28 Section 5-4 - Back End Processor (BEP)
5-4-12-5 USB to Serial Adapter Cable Setup (RS232 Serial Port Connector on the External I/O)
The Prolific USB to RS232 Adapter Cable (black one) should be properly set up when the Base Image 
Load is applied to the system. However, if you need to set a specific parameter for the USB COM Port 
(COM1) perform the following steps:
- After booting up with the Service Dongle, entering Maintenance Mode and Windows, select 
My Computer>Properties>Hardware Tab>Device manager.
- Under Ports (COM & LPT) select “Prolific USB-to-Serail Comm/Port (COM 3)” and select 
Properties.
- Under the Port Settings TAB you can set the Bits per second, Data bits, Parity Stop Bits and 
Flow Control to the desired values.
5-4-13 Outputs
Table 5-9    Factory Default Values
Signal NameSetting
Bits Per Second 9600
Data Bits 8
Parity None
Stop Bits1
Flow ControlNone
Table 5-10    Output Signals 
Signal NameDescriptionSignal Path 
+5VDC DC Voltage PC2IO > IIO
+12VDC DC Voltage PC2IO > IIO
PS_ON* TBD (Active Low) PC2IO > IIO > Card Rack
StandbyTBDPC2IO > IIO > Top Console
SVideoSVideo OutPCVIC > PC2IO > IIO > EIO
CVideoComposite Color VideoPCVIC > PC2IO > IIO > EIO
VGA VGA High Resolution Video to External Video Screen PCVIC > PC2IO > IIO > EIO
VGAVGA High Resolution Video to Internal Video Screen (Top 
Console)BEP > Top Console
BW Video RGBBW Video from RGB. 
This signal is not used on LOGIQ™ 9PCVIC > PC2IO > IIO > EIO
This signal is not used on LOGIQ™ 9
Audio Out Audio Out from BEPBEP > IIO > Internal VCR
BEP > IIO > EIO > External VCR
TRIGVideo Trig SignalPC2IO > IIO > EIO 
						

							GE MEDICAL SYSTEMS PROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL 
Chapter 5 Components and Functions (Theory) 5-29
5-4-14 BEP Power On Path
(refer to Figure 5-20 on page 5-29 )
The Back End Processor is powered ON by: 
- Press and release the OP I/O Standby (On/Off) switch. 
- The signal from the OP I/O goes to the II/O (A4) and through the rack power relay in the 
Internal I/O.
- The PC Power ON signal from the II/O (B6) goes to the PC2IO (D2) then to the BEP 
motherboard commanding the BEP Power Supply to turn ON.
Figure 5-20  BEP Power On Path 
						

							GE MEDICAL SYSTEMSPROPRIETARY TO GE
D
IRECTION 2294854-100, REVISION 3  LOGIQ™ 9 PROPRIETARYMANUAL   
5-30 Section 5-4 - Back End Processor (BEP)
5-4-15 BEP Power Off Path
(refer to Figure 5-21 on page 5-30 )
The Back End Processor is powered Off by: 
- Press and release the OP I/O Standby (On/Off) switch.
- The signal from the OP I/O goes to the II/O (A4) and through the rack power relay in the 
Internal I/O to the I
2C register.
- Software detects the request to power down via the I
2C buss from the II/O (B5) to the BEP 
(D1).
- The system begins a controlled shut down procedure closing applications, files, turning off FE 
rack power and finally BEP power.
Figure 5-21  BEP Power Off Path