Toshiba Strata Dk14, Dk40i, Dk424 Installation And Maintenance Manual

							Strata AirLink Systems
RWIU System Installation
Strata DK I&M 5/9916-49
Strata AirLink Systems
3. Press t until SYSTEM 
CONFIG.
 
displays
...or 
 + )&1.
4. Press 
)&1.
5. Enter the proper System ID 
(SID).
NoteThe SID must match the data entered in the system 
settings.
6. Press 
&/5to make 
corrections.
7. Press 
t.
8. Enter the handset ID (four 
digits) for the system ID 
entered in Substep 5.
9. Press 
t for other systems.
10. Repeat Substeps 5~7 to enter 
all the system and handset 
IDs required.A maximum of eight system IDs and associated handset 
IDs can be stored in handset memory.
11. Press 
(1. The ESN displays momentarily.
12. Press 
&$//. The handset ESN is stored in the BSIA.
SYSTEM
CONF IG.
12 : 15
SID#0
12 : 15
HID#0
12 : 15
HID#1
12 : 15 
						

							Strata AirLink Systems
RWIU Additional Information
16-50Strata DK I&M 5/99
RWIU Additional Information
The following paragraphs describe:
©RWIU/WWIS interface unit
©Changing the initial configuration
©Changing the communications port
©Checking the RWIU and Base Station software versions
©Viewing log messages
©Resetting the Base Stations and RWIU
©Upgrading the RWIU and Base Stations
©Changing the Base Station number
RWIU/WWIS Interface Unit
The Strata AirLink Wireless System interfaces to Strata DK16, DK16e, DK40, DK40i, DK280, 
and DK424 systems with an RWIU Interface Unit. The RWIU PCB (shown in Figure 16-29) 
functions as a protocol converter between the Base Stations on one side and the Strata DK system 
on the other. The RWIU is the “master” PCB, generating timing and synchronization signals and 
the WWIS PCB is the “slave.”
The PCBs have LEDs that indicate a continuous status of operation for both. They are shown in 
Figure 16-30 on Page 16-52. The switches and jumper are described in Tables 16-11~16-13 on 
Page 16-37.
The PCB has an Intel® 80C186EC, 25 MHz (provided by a 50 MHz oscillator), 16-bit 
Complementary Metal Oxide Semiconductor (CMOS) embedded Central Processing Unit (CPU) 
with the following:
©External 16-bit data bus and 20-bit address bus
©Four Direct Memory Access (DMA) channels
©Three programmable timer counters
©Eight programmable external interrupt controller inputs
©Two integrated communication channels Universal Asynchronous Receiver/Transmitter 
(UARTS)
©Integrated Watch Dog Timer (WDT)
©Two flash memories (expandable by two)
©Two CMOS Static Random Access Memories (SRAMs) (expandable by two)
©In-circuit test points
The RWIU has the following interfaces:
©Backplane (P1)
©Synchronous RS485 bus (J5)
©Serial line (J7)
©External power supply (J8)
©JTAG Mach programming (J11) 
						

							Strata AirLink Systems
RWIU Additional Information
Strata DK I&M 5/9916-51
Strata AirLink Systems
The WWIS has four Base Station interface connectors (J1~J4).
Figure 16-29 Top and Side View of the RWIU
The CPU addresses come from three octal latches that are also address buffers while the data bus 
addresses are buffered by a pair of bi-directional octal transceivers connected to the various 
peripheral devices.
There are eight external interrupt signals:
©INT0 – connects to the data highway receive (RX) and transmit (TX) interrupt output or to the 
RX interrupt output of internal serial channel one (optional).
©INT1 – connects to the TX interrupt output of internal serial channel one.
©INT2 – connects to interrupt output of the DMA channel N0 (DMA0).
©INT3 – connects to interrupt output of the DMA channel N1 (DMA1).
©INT4 – connects to N0~3 interrupt output.
©INT5 – connects to the RX interrupt output of internal serial channel one or to the data 
highway RX and transmit TX interrupt output (optional).
©INT6 – connects to the general device interrupt output.
©INT7 – connects to the interrupt output of the optional external UART device.
The CPU has two flash (boot) memories, 128KB each, operating at 55 ns and mounted on 32-pin 
sockets. The memory is expandable to two optional flash memories (512KB each, 55 ns). The total 
size of program memory is 256KB or 1024KB using two memories.
The Random Access Memory (RAM) consists of two CMOS SRAM chips, 128KB (55 ns), used 
as main data memories. It is expandable to 512KB (55 ns) using two additional chips. The total 
size of the data memory of the CPU is 512KB.
3721
RWIU1A
12345678ECE
ON
S1
12345DIP
ON
S2 S3
J7 J9JP1
J10 J12 J13J15 J14 J17 J16J13
LD2 LD1 J8JTAG12 ON
RWIU (top view)
RWIU (side view) 
						

							Strata AirLink Systems
RWIU Additional Information
16-52Strata DK I&M 5/99
The WWIS PCB (see Figure 16-30) has the following components:
©Four E1 transceivers with crystals, line transformers, protectors, and electronic circuit 
breakers
©Two LEDS for each transceiver
©Eight elastic buffers, two for each E1 interface
©Surface Mount Technology (SMT) resistors and capacitors
Figure 16-30 Top and Side View of WWIS
The thickness of the RWIU is 1.6 mm and the maximum distance between the WWIS PCB 
(including the height of the mounted components) is 30 mm.
Signaling
A high density Mach decoder generates all the chip select signals and control signals for Erasable 
Programmable Read Only Memory (EPROM), flash and RAM memories, peripherals, and Input/
Output (I/O) devices. The Mach device includes a serial interface on connector J7 for on-board 
programming.
The digital I/O block has two digital input buffers and four output D flip-flops for the digital 
output signals. All input buffers and output flip-flops connect to the CPU lower data bus using a 
bi-directional transceiver. All control signals are generated to the I/O devices by the Mach decoder.
A power ON external reset generator is provided by an internal WDT chip. There is also a power-
fail circuit that alerts the CPU when the voltage falls below 4.75V. This feature is necessary 
because the CPU stores data in the backup memory of the RTC during a power failure.
An RTC chip mounts on the RWIU PCB only. It has an internal Lithium battery and an internal 
backup 2KB of SRAM memory, powered by the same Lithium battery.
The RWIU interfaces to the Strata DK system using a 32 time slot, 2.048 MHz Pulse Code 
Modulator (PCM) channel. The PCM channel has the following signals:
©PHOUT – 32 time slots (receiving data)
©PHIN – 32 time slots (transmitting data)
©PHFS – 8 KHz frame synchronization output
3722
J4
LED4 LED3 LED2 LED1J3 J2 J1P16 P17
P14 P15
P13
P12 P9 P10
WWIS1ATOSHIBA
WWIS (top view)
J4
LED4 LED3 LED2 LED`J3 J2 J1
WWIS (side view) 
						

							Strata AirLink Systems
RWIU Additional Information
Strata DK I&M 5/9916-53
Strata AirLink Systems
©PHCLK - 2.048 MHz clock input
©4MCLK - 4.096 MHz clock input
The interface with the voice channel has the following signals:
©PCM matrix memory time switch device
©Digital I/O buffers (output enable)
The PHOUT connects to the matrix PCM input signal using a digital input buffer. The PHIN 
connects to the output signal using a digital output buffer. It is enabled only during the 
transmission phase of the data by the matrix. A time-slot assignment logic enables the output 
buffer of the PHIN signal during the right time segment.
There are five hardwired address pins coming from the backplane connector (P1) of the RWIU and 
one additional two-position DIP switch (S3). These are connected to seven input pins to control 
the time-slot assignment logic for the various configurations. The CPU reads the status of these 
hardwired addresses and the state of the two-position DIP switch (S3). An additional five-position 
DIP switch (S2) selects various RWIU configurations and synchronizes the clock with the 8 KHz 
frame synchronization pulse.
The receive data signal from the main PCM voice channel connects to input N0 (IN0) of the 
matrix. The transmit data signal from the main PCM voice channel comes from output N0 
(OUT0). The signal connects to a buffer that generates the external buffered transmit data signal 
available on the backplane connector P1. Table 16-19 describes the four internal synchronous 
2.048 PCM busses generated by the matrix.
Table 16-19 Generated Internal Synchronous PCM Signal
PCM Bus 
NumberE1 InterfaceSignal
1N1RD01 internal synchronous PCM channel N1 receive data.
XDI1 internal synchronous PCM channel N1 transmit data 
signal, derived from input N1 (IN1) of the matrix while the 
output signal is derived from output N1 (OUT1) of the 
same matrix.
2N2RD02 internal synchronous PCM channel N2 receive data.
XDI2 internal synchronous PCM channel N2 transmit data 
signal, derived from input N2 (IN2) of the matrix while the 
output signal is derived from output N2 (OUT2) of the 
same matrix.
3N3RD03 internal synchronous PCM channel N3 receive data.
XDI3 internal synchronous PCM channel N3 transmit data 
signal, derived from input N3 (IN3) of the matrix while the 
output signal is derived from output N3 (OUT3) of the 
same matrix.
4N4RD04 internal synchronous PCM channel N4 receive data.
XDI4 internal synchronous PCM channel N4 transmit data 
signal, derived from input N4 (IN4) of the matrix while the 
output signal is derived from output N4 (OUT4) of the 
same matrix. 
						

							Strata AirLink Systems
RWIU Additional Information
16-54Strata DK I&M 5/99
Timing and Synchronization
To comply with FCC part 15D clock and frame synchronization requirements, the clock and frame 
frequency accuracy must be ± 10 parts per million (ppm). To meet this requirement without adding 
cost, the system uses the Strata DK system as the primary clock source. The analog, digital, and 
Stratum 3 trunks were considered as possible configurations.
To continue using only one single interface between the RWIU and the Base Stations, the clock 
signal is sent through the E1 interface using a 320 ms synchronization pulse. The Base Stations 
lock onto the RWIU clock signal and the Portable Unit Board (PUB) extracts the clock from the 
Base Stations. The RWIU provides a signal to all other PCBs for a simple insertion into the E1 
time slot 17.
Backplane Interface Connector
The RWIU has a 44-pin Deutsche Institut fur Normung (DIN) connector (P1) that connects to the 
backplane of the Strata DK system. The connector has two rows with 22 pins in each row.
 PBX Data Highway Interface
The PBX data highway control channel uses an integrated UART controller running at 312.5 kbs. 
The control channel uses the following signals that originate from the backplane connector P1:
©DHOUT - receive signal (input) and connects to RX
©DHIN - transmit signal (output) and connect to TX
The UART debug serial channel connects to the integrated serial channel N0, and the 
asynchronous multi-drop communication channel connects to serial channel N1. The UART 
internal serial channels connect to the debug serial channel and the asynchronous multi-drop 
communication channel. The debug serial channel connects to N0, and the asynchronous multi-
drop communication channel connects to the external UART device.
An RS-485 asynchronous multi-drop communication link between the RWIU and the WWIS 
occurs because the UART connects to the CPU external bus. The UART is not physically mounted 
on the RWIU, but uses the 28-inch PLCC socket on the RWIU.
The UART receives its operating frequency from the output of the internal timer N0 of the CPU. 
N0 is programmed to divide the internal 25 MHz operating frequency of the CPU by a factor of 5 
to obtain the UART 5 MHz operating frequency. It is possible to use N0 for other software 
applications by substituting an optional external 5 MHz crystal.
Base Station Interface Connectors (E1s)
Four identical long-haul E1 (2048 kbs) PCM interfaces connect the RWIU PCB to each Base 
Station (N0~N3) using a standard pulse (see Table 16-20). Each interface has:
©Primary access transceiver devices
©Two elastic buffers for each E1 channel
©RX and TX line transformers with protectors
©320 ms synchronization signal insertion logic (channel N17)
©Loop back controls
©RWIU generated Base Station reset (relays K1~K4)
©RFI protectors (common mode chokes - optional) 
©Electronic circuit breakers for each E1 channel 
						

							Strata AirLink Systems
RWIU Additional Information
Strata DK I&M 5/9916-55
Strata AirLink Systems
The four primary access transceivers (U7, U13, U25, and U35) use the E1 (31 B + D) interface to 
each Base Station. Not all of the 32 time slots of the E1 (32 B + D) frame are used. The format is 
called 8 B + D and organized as follows:
©Time slot N0 – synchronization time slot
©Time slots N1~N8 – voice channels time slots
©Time slots N9~N15 – idle (free) time slots
©Time slot N16 – signaling CCS time slot
©Time slot N17 – multiframe 320 ms synchronization pulse time slot
©Time slots N18~N31 – idle (free) time slots
Table 16-20 Connector J1~J4 Descriptions
J4
Pin No.Base StationNameDescription
1
1TX_TIP_BS1
E1 interface (transmission output from TX line 
transformer)
2 TX_TIP_BS1
3 Not used
4 Not used
5 RX_TIP_BS1
E1 interface (transmission output from RX line 
transformer)
6 RX_TIP_BS1
J3
1
2TX_TIP_BS2
E1 interface (transmission output from TX line 
transformer)
2 TX_TIP_BS2
3 Not used
4 Not used
5 RX_TIP_BS2
E1 interface (transmission output from RX line 
transformer)
6 RX_TIP_BS2
J2
1
3TX_TIP_BS3
E1 interface (transmission output from TX line 
transformer)
2 TX_TIP_BS3
3 Not used
4 Not used
5 RX_TIP_BS3
E1 interface (transmission output from RX line 
transformer)
6 RX_TIP_BS3
J1
1
4TX_TIP_BS4
E1 interface (transmission output from TX line 
transformer)
2 TX_TIP_BS4
3 Not used
4 Not used
5 RX_TIP_BS4
E1 interface (transmission output from RX line 
transformer)
6 RX_TIP_BS4 
						

							Strata AirLink Systems
RWIU Additional Information
16-56Strata DK I&M 5/99
The E1 devices receive each processed (but not formatted) 31 B + D frame from the CPU and 
transmits it (after formatting) to its Base Station through its TX line transformer. The same is true 
from the receiving side. The CPU performs the protocol conversion. Both TX and RX transfers are 
actuated in DMA mode by the CPU.
The E1 device connects to the matrix using four internal 2048 kbs synchronous PCM buses with 
the following signals:
©RD01 internal PCM channel n1 received data (U7)
©XDI1 internal PCM channel n1 transmit data (U7)
©RD02 internal PCM channel n2 received data (U13)
©XDI2 internal PCM channel n2 transmit data (U13)
©RD03 internal PCM channel n3 received data (U25)
©XDI3 internal PCM channel n3 transmit data (U25)
©RD04 internal PCM channel n4 received data (U35)
©XDI4 internal PCM channel n4 transmit data (U35)
The four internal 2048 kbs synchronous PCM busses transfer the data between each E1 device and 
the matrix. The matrix places the data on the backplane PCM channels.
Protectors
The RX and TX transformers connect to the E1 line through protector devices. Current-limiting 
resistors are used on both sides of the transformers. Tranazorb U45~U47, U53, U57~U58, and 
U62~U63 and Gas Tubes G1~G8 devices provide fast protection from lightning by sending 
sudden surges to the frame around the RWIU PCB.
Additional protection is provided by the secondary line transformers by dual MMBT7000 diodes. 
All the line transformers RX and TX are breakdown-rated at 1500 Vrms. Loop back controls and 
Base Station resets are provided for each Base Station by a relay. Each relay is controlled by the 
CPU using an output port signal. Transistors drive each relay.
Power (-40VDC) transfers from each Base Station to the associated remote Base Station are 
performed using a standard phantom interface on the central taps of the secondary of each TX and 
RX transformer of the E1 interface. An electronic circuit breaker with associated power Field 
Effect Transistor (FET) is used for each Base Station E1 interface.
Important!In the case of a short circuit on the -40VDC side of one the phantom interfaces, the 
electronic breaker turns off its associated power FET. After about five seconds, it 
tries to verify that the short is gone by turning on the power FET for a shorter 
period (about 200 ms). If the short is gone, the circuit breaker turns on its power 
FET permanently. If the short is still present, it continues to retry the circuit. 
The same device protects the PCB against a rush current at Base Station power up. Each electronic 
circuit breaker block is turned on/off by the CPU using the output port that drives the LED of a 
photocoupler. A short circuit indication flag is provided to the CPU for each electronic circuit 
breaker. The following are additional protection devices for each E1 interface:
©Four slow-blow fuses
©One polyswitch 
						

							Strata AirLink Systems
RWIU Additional Information
Strata DK I&M 5/9916-57
Strata AirLink Systems
Ring Back Tones Generator
The RWIU PCB incorporates a 32KB EPROM that generates:
©440 Hz ring back tone, modulated at 480 Hz
©2400 Hz busy override tone
©4 tone channels for the U.S.
Each tone generates 800 bytes every 125 ms. The bytes are sent on a specific time slot of the 
matrix and to the related time slot of the PHIN output.
Serial Line Interface
There is a six-pin serial line interface (J7) that debugs and sets up the system. It is a RS-232 port 
and connects the PC to the RWIU (see Table 16-21).
Software Architecture
The RWIU software is a real-time embedded software, written in C language designed for the Intel 
80186EC processor. Its modules include real-time tasks, service packages, and hardware drivers. 
Its functions are:
©Communication (KSU DHWY and Base Station)
©Local debugging
©Monitor communication
©Call control logic procedures (call origination, delivery and release)
©Mobility control (handoff)
©Handset text and icon displays
©System and Base Station power up controls
©RWIU cross connects
©Base Station software download
©Start-up diagnostics (BIT)
©Online diagnostics
©Loop tests
©System audit and parameter refresh
©RWIU and Base Station configuration
©Alarm reports and LEDs
Table 16-21 Connector J7 Descriptions
Pin No.NameDescription
1 TXD RS-232 TX data (from the RWIU)
2 RTS_0 RS-232 RTS data (from the RWIU)
3 RXD RS-232 RX data (to the RWIU)
4 CTS_1 RS-232 CTS data (from the RWIU)
5 Not used
6 GND RS-232 Ground (from the RWIU) 
						

							Strata AirLink Systems
RWIU Additional Information
16-58Strata DK I&M 5/99
©System parameters
©UTAM activation
The software is built in layers, each implementing a different function. Each layer gets input from 
the layer below and provides services to the layer above. The hardware drivers layer uses 
interrupts and API calls interface with the layers above.
The operating system is totally independent of the hardware configuration and uses API calls to 
interface with the other layers. All other layers use API calls and inter-task communication 
messages to interface each other.
The operating system main services are:
©Task definition and initiation, termination, and context switching
©Inter-task communication (message, semaphores)
©Message handling (mailbox)
©Timers
©Memory management (buffer pools) 
All access to the operating system is performed using an Operating System Shell (OSS). The shell 
provides a general API to the operating system services. The software supports the following 
interrupt-driven protocols:
©KSU DHWY communication protocol (addressed ASYNC)
©Base Station communication protocol (E1 D channel)
©Local debug/monitor communication protocol (RS-232)
The main data structures are:
©Port information
©Card status
©External E1 links state and status
©External/internal E1 cross connect configuration
©Base Station configuration
©System ID
©UTAM parameter
The communication protocol layer, using the corresponding hardware drivers, handles external 
interfaces. Messages from the KSU and the Base Station are converted by the communication 
protocol layer to inter-task messages and are sent to the corresponding layer or task. The hardware 
drivers consist of:
©CPU (Intel 80186EC)
©E1 Transceiver (DALLAS DS2153)
©Matrix (MITEL MT8985)
©WDT (CPU)
©UART (16550 compatible and internal to the CPU) 
©External UART (16550 compatible)
©PIC (8259 compatible and internal to the CPU)