GTE Omni Si Database Technical Practices Issue 1 Manual

							TL-130500-1001Table 4.1
Memory Cross-Reference Get Started FileChannel Memory to EPCMN Network Memory Cross-Reference
Group 0 Slots AO, A2, A4, 
A5, A7, A9, Group 1 Slots BO, B2, B3, B5, B6, B7
AlO, All
B8, B9, BllChannelEPCMN Network Memory Channel EPCMN Network Memory
Memory
Memory
CMA
CMBPAD
04. . .CMACMBPAD
08. . .OA. . .oc. . .04. . .08. . .OA. . .oc. . .
CH 00. .oo
. . .00. . .01. . .
02CH 01. . 
.04
. . .08. .05. .OACH 02. . 
.08. . .
10. .09. . .12CH 03
. . .OC
. . .18. . .OD. . .1ACH 04. . 
.lO. . .20. . .11. . .22CH05. . 
.14
. . .28. .15. .2ACH06. . 
.18
. . .
30. .19. . .32CH 07. . 
.lC. ..38. .1D
. . .3ACH 08. . 
.20. . .
40. . .21. .42CH 09. . 
.24. . .
48. .25. . .4A
CHlO . ..28. . .
50.29. . .52
CHll< . ..2C. . .
58.2D. .5ACH12 . ..30
. . .60. . .31. . .62CH13 . ..34
. . .68. . .35. .6ACH 14. . 
.38
. . .70. . .39. . .72CH 15. . 
.3C. . .78. .3D
. . .7ACH16 . ..40
. . .
80. .41. . .82CH17 . ..44
. . .88. .45. .8ACH18 . ..48
. . .90. .49. .92
CH19 . ..4C. . .98. . .4D. . .9ACH 20. . 
.50
. . .A0. . .51. . .A2CH 21. 
.54. .A8. . .55.AA
CH 22. . 
.58
. . .BO. . .59. .B2CH 23. 
.5C
. . .B8. .5D. .BA
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Table 4.2Memory Cross-Reference Expansion File
Channel Memory to EPCMN Network Memory Cross-ReferenceGroup 4 Slots Cl 
- C6Group 5 Slots C7 - Cl 1
ChannelEPCMN Network Memory Channel EPCMN Network Memory
MemoryMemory
CMACMBPAD .CMACMBPAD
02.. .
08.. .OA. . .OC. . .02.. .08. . . OA. . .oc. . .
CH 00. .OO
. . .01. . .01. . .03CH 01. . 
.04
. . .09. . .05. . .OBCH 02. 
.08. . .11. ..09. . .13CH 03. . 
.oC
. . .19. .OD. . .1BCH 04. . 
.lO. . .21. . .11. . .23CH 05. . 
.14
. . .29. . .15. . .2BCH 06. 
.18. . .31. . .
19. . .33CH07. . 
.lC. . .
39. . .1D. . .3BCH 08. 
.20. . .41. . .21. ..43CH 09. . 
.24. . .
49. . .25. ..4B
CHlO . ..28. . .51. . .29. . .53
CHll . ..2C. . .59. . .2D. . .5BCH12 . ..30
. . .61. . .31. . .63CH13 . ..34
. ..69. . .35. . .6BCH 14. . 
.38. . .71. . .39. . .
73CH15 . 
..3C. . .79. .3D. . .7BCH16 . ..40
. . .81. . .41. . .83CH17 . ..44
. ..89. ..45. . .8B
CH18 . ..48. ..91. ..49. . .93
CH19 . ..4C. . .99. ..4D. . .9BCH 20. . 
.50
. . .Al. . .51. ..A3CH 21. . 
.54. .A9. .55. ..AB
CH 22. 
58. . .Bl. ..59. . .
B3CH 23. . 
.5C. . .B9. ..5D. . .
BBs-74
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Table 4.2Memory Cross-Reference Expansion File
Channel Memory to EPCMN Network Memory Cross-Reference (Continued)Group 6 Slots DO 
- D5
Group 7 Slots D6 - DllChannelEPCMN Network Memory Channel EPCMN Network Memory
Memory
Memory
CMA
02. . .CMBPAD
CMACMBPAD08. . .OA. . .oc. . .02. . .08. .OA. .
oc. . .
CH 00. 
.02
. . .
05. . .03.07CH 01. 
.06
. . .OD. . .07. .OFCH 02
. . .OA
. . .
15. . .OB. .17CH 03
. . .OE
. . .1D. . .OF. . .1FCH04 . ..12
. . .25. . .13. .27CH 05. . 
.16
. . .2D. . .17
. . .2FCH 06. 
.lA. .35. . .1B. .37CH 07. . 
.lE. . .3D. . .1F. .3FCH 08. . 
.22
. . .
45. . .23. .47CH 09. . 
.26
. . .4D. . .27.4FCH 10. . 
.2A. ..55. . .2B.57
CHll . ..2E. . .
5D. .2F. .5FCH12 . ..32
. .
65. . .33. .67CH13 . ..36
. .
6D. . .37. .6FCH 14. 
..3A. ..75. .3B
. . .77
CH15 . ..3E. . .7D
. . .3F.7FCH 16. . 
.42. ..85. . .43.87CH17 . ..46
. . .
8D. .47.8FCH18 . ..4A
. . .95. . .4B
. . .97
CH19 . ..4E. .9D. .4F. .9FCH 20. . 
.52. .A5.53.A7CH 21. . 
.56. .AD. . .57. .AFCH 22. . 
.5A. .B5. . .58. . .B7CH 23. . 
.5E
. . .BD. . .5F. .BF
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Each time slot also includes other memories not yet discussed:
control memory B, pad memory and some extra memory
locations allocated to information memory. The purpose of these
memories follows:
Control Memory B4.3.3 Control memory B accommodates three-way conference
calls. This is done as follows:
1. The third party (phone off-hook) has been assigned a different
time slot; and, in this arrangement, each time slot contains the
information memory address of the other two time slots (one
address in control memory A, and the other in control memoryB).2. A threshold detector, based on voice volume, determines
which information memory data will be selected for a data
sample.
a. If the data sample in the information memory address
associated with control memory B represents a louder
volume level than the data sample associated with control
memory A, control memory B will be used,
b. If the volume is lower, then control memory A is normally
used.In summary, the detector decides which control memory (A or B)
is used, and the contents of control memory determine which
time slot is used. During a simple two-way conversation call,
control memories A and B both contain exactly the same
information.
Pad Memory4.3.4 Pad memory contains data bits which are used to select
the amount of attenuation (pad) to be applied to the data being
transferred through the connection. It reduces the volume of
nearby (loud) sources, thereby providing a uniform volume level
between different types of connections.
Information Memory4.3.5 Information memory has extra memory locations (Figure
4.4) which contain data bits that represent various tones (dial
tone, 
ringback tone, busy tone, quiet tone, DTMF tones, etc.)
used by the system during call processing. Tones are issued by
the system information as follows:
1. When a station goes off-hook, the system connects a dial
tone to that subscriber as a signal to begin dialing.
2. Connection is made by writing the address of the location in
information memory (time slot number), where the dial tone
data is stored, into control memory.
3. When the subscriber dials the first digit, the instrument is
connected to quiet termination (another location in information
memory).
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4. The process continues until the subscriber connects to the
information memory address that is associated with the time
slot assigned to the party being called.Line Card Interface4.4 Transmission of voice/tone signals through the time-switch
network is performed using time-division multiplex techniques
and by collecting samples of the input signal
1. The incoming signal passes through to the CODEC converter
circuits on the line card.
2. A digital sample is taken and put onto the PCM IN bus (an 
S-bit serial-line bus).
3. The PCM IN bus passes the data into the 
PCMI card which
converts serial PCM to 8-bit parallel PCM.
4. The data passes to the information memory at the address for
the time slot that has been assigned to the hardware (station)
generating the input signal.
5. A sample is collected and the data in that information memory
address is updated 8,000 times per second.
Digital Line4.4.1 The digital voice/tone signal is retrieved from the above
Card Interfaceinformation memory address, using a different method and route.
1. The control memory of the time slot that has been assigned to
the station being called (destination) contains the information
memory address of the data which is to be retrieved.
2. This data is inserted onto the PCM bus and delivered to the
appropriate 
PCMI card and, eventually, to the appropriate line
card.
3. Like the analog process, this occurs 8,000 times each second,
which enables the smoothing samples by the filtering circuit to
produce an analog signal.
4. This restored analog signal is output from the filter circuit and
then passed on through the 
SLIC hybrid.
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Time Slot Group4.4.2 In the system, each group has 24 time slots or channelsDivision(Figure 4.6). The channel memory connects to the EPMN
(Expanded Pulse Code Modulation Network) card by front tab
plug-in cables and uses one-half of the EPCMN card
containing information memory. Therefore, 24 time slots per
group times 6 groups per system equals 144 time slots. See
Section 10.0 for more information on time slots.
I-PCMUS GROUP C 48 TIME SLOTS--IFILE A
f24-t--4-
:::::;12345678901 2222222223333 2 34 33 53 6
TBieSlUlS
FlfETOTAL
COMMON CONTROL
p,$II
FILE B
-lSlOlSPCMUS GROUP D48 TIME SLOTS
Ti%SIOIS
FI=LETOTAL
24 TIME SLOTS
I
S-78
Figure 4.6Time Slot Group Divison
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							TL-130500-1001Network Hardware4.5 The time-switch network is a self-sustainina ooeration. It
A
M
PL
IT
UD
E
A
ND
P0
L
A
RI
T
Y
10
a
64
2ZERO
-2
-4
-6
-8-10
-12
Operationcontinuously performs memory reading functiois and acts on the
data obtained without intervention from the system
microprocessors. Once the system microprocessor has written
instructions into the time-switch network memories for a given
phase of any call progression, no further intervention is required.
The 
INCKS (Synchronizable Intermediate Network Clock) card
continuously sends out addresses from a time-slot counter to
control/synchronize this function. The system samples each
active circuit 8,000 times per second which is equivalent to
sampling every 125 microseconds. Figure 4.7 shows an
example of an analog signal being sampled. The resulting output
is shown in Figure 4.8. Figure 4.9 showes the file bus with
samples present.
I
SW 5210SAMPLE GATE OUTPUT FROM THE ANALOG SIGNAL
TIME-125 MICROSECONDS
l-l
I
MSAMPLES
11 12
Figure 4.7Sampling an Analog Signal
8187s-79 
						

							TL-130500-1001LIa
Tu6
D
E4
A2NZEROD
LA
-6
RI-aT
Y-10
-12ANALOG SIGNAL BEING SAMPLED
TIME+
Figure 4.8Sampling an Analog Signal
- II -5.18 MICROSECONDS
PER CHANNEL IN EACH FILE
CHANNEL
00000000001111111111 22220000000000111111llll22220000NUMBEH01234567890123456789 01230123456769012345676901230123erc
,o I- 125MICROSLCONDS ---Ia
6
4
l-l
#2#32E FADEAZERO
-2DGEl c1G
-4
-6
-8-10f i-Y-r
A = PRECEDING ANALOG SAMPLE AS IT APPEARS ON THE PCM BUSB.C,D. ETC = OTHER ANALOG SAMPLES FROM OTHER FILE INTERFACE
Figure 4.9File Bus with Samples Present
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The INCKS card provides 8-phase sequences or synchronizing
intervals for each cycle so that its base rate is 49.408 MHz. The
PCMTS (Pulse Code Modulation Tone Source) card and the
EPCMN card are time-synchronized by the INCKS card. The
instantaneous digital equivalent of the tone samples are loaded
into information memory addresses 192 through 255
(hexadecimal CO through FF) during every pass of time slots 64
though 128. Both EPCMNs repeatedly sequence time slots 1
through 192. Thus, during each time slot, new PCM data is
written into the information memory (hexadecimal addresses 00
through BF) of the EPCMN card (network). Consequently, the
EPCMN stores, accesses, and controls information from 144
differenttime slots and 64 different tones. The EPCMN card also
passes on timing signals from the 
INCK card to each CHM85
card to complete the time synchronization sequence.
Once the CHM85 has accepted the PCM data from the network,
the system can complete the remainder of the connection. The
CHM85 places this PCM data on the PCM bus and strobes the
data into the proper 
PCMI card for parallel-to-serial
conversion. The CHM85 card also directs the PCMFS card to
access the correct PCMUS and circuit, and then enables the
PCM gate in synchronism with the PCM signal. The circuit,
associated with this active time slot then begins the filtering
process on the amplitude signal just received. It will be 125
microseconds before the next sample is received by this circuit.
During this time, the network will perform the above described
actions for the other 191 time slots and returns to perform this
time slot’s time-switching actions..
Network Clock Card4.6 To have a slaved-clock, a INCKS (Synchronzable
Intermediate Network Clock) card (FB-20922-A) (Figure 4.11)
must be placed in the system. The clock synchronization
hardware on the INCKS card provides for monitoring four
external 
1.544-MHz clock signal inputs (SINXO to SINX3) on the
card handle. One of the input clock signals is selected by the
card and used for frequency synchronization. The clock card will
remain locked on an input until it determines that the clock signal
has missed a pulse or has been disabled completely. When the
SINX input that the clock card is locked onto fails, the card
begins scanning the four inputs for a valid clock input. When it
finds a good 
SINX input, the card will frequency-synchronize
onto that 
SINX input.
When the INCKS card is not locked onto an external 
Tl clock
signal, it assumes master configuration and reverts to the system
clock. When a valid input is detected, the card locks onto the
external clock, cancels its free-running mode, and
resynchronizes to the new input. When the INCKS card is in its
free-running mode, the system is synchronized to the 
free-running clock frequency. When the INCKS card locks onto a
SINX Tl input, the system is synchronized to the Tl input and
functions in the slave mode.
S-828187SVR 5210