GTE Omni Si Database Technical Practices Issue 1 Manual

							SVR 5210TL-130500-1001
CP85E3.4.5 The Central Processor Unit card contains an INTEL 8085
FB-17288-Amicroprocessor and associated clock, control, interrupt, and I/O
(InpuVOutput) interface circuits. The 8085 microprocessor
provides both normal switching and MDR functions. The card
controls all operations within the system including:
l Path connect/disconnect within the network
* Data transfer to/from system maintenance terminals
l Data transfer to/from system disk drive
l Communications to/from system peripherals
The 8085 makes decisions based on the various inputs including
an 8-level system interrupt structure. It controls the operations
such as peripheral interface scanning, data sampling routine,
and message transfers. This card contains a 512 word by d-bit
ROM (read-only memory), which contains the system bootstrap
loader and CPU self-test software. The card also contains the
system watchdog timer circuitry as well as circuitry for
addressing data and control signals. Communication with other
subsystems is through a 
16-bit address bus, an 8-bit data bus,
and control signal lines.
MPB853.4.6 Each file in the system requires a Multi-Processor
FB-17215-A
Buffer card. This MPB85 card enables the equipment contained
in the Get Started File or the Expansion File. Once enabled, the
equipment receives control and sensing signals from the CPU
and the 
PCBs within the PCM universal slots:
l Circuitry on MPB85 in the Get Started File performs
control/sensing functions for groups A and B.
l Circuitry on MPB85 in the Expansion File performs
control/sensing functions for groups C and 
D.MPB85 provides interfacing circuitry to the 
Tl span circuitry,
which can be equipped in group C of the Expansion File.
NSDC3.4.7 The Narrow Serial Device Controller card is optional.
FB-20992-AThe NSDC provides 
t~vo independent serial interface ports that
are cable-connected to modems and/or terminals external to
the equipment cabinets. The NSDC is addressed via the CPU
address bus, and data is transferred between the CPU and
NSDC via the CPU data bus. Data transfers can be programmed
as 
I/O or interrupt-driven.
Each port can be configured for
current loop or EIA (W-232-C) operation. Full-duplex,
synchronous, and asynchronous communication is allowed.
Typically, the NSDC card is connected via a cable to the system
maintenance terminal.
8i87s-43 
						

							TL-130500-1001FMSD3.4.8 The File Management System Data card provides an
FB-17220-BOAintelligent serial data interface between the floppy disk drive, the
hard disk drive, the PD-200’s ADMP, and the CPU. Data and
control signals are cable-connected between the floppy disk
drive and FMSD. The FMSD is addressed via the CPU address
bus. Data is transferred between the CPU and the FMSD via the
CPU data bus. This card provides DMA (Direct Memory Access)
and interrupt control to the CPU.
The FMSD contains the following major circuitry:
0 Floppy disk control interface logic
Q SASI bus interface logic
0 DMA interface logic
o 8085 microprocessor, on-board memories, and associated
clock,
TPl23.4.9 The Test Panel Interface card permits communication
FB-17188-Abetween the system CPU and the optional Type 200 Test Set.
Serial, address, data, and control signals are cable-connected
between the TP12 and the test set. The TP12 is addressed via the
C?U address bus. Data is transferred between the CPU and the
T 
‘12 via the CPU cata, address, and control buses. A manual
switch on the test set generates an interrupt signal that is sent to
the CPU via the 
TPl2 when the test set is activated.
TL-I 30200-l 004 describes the test set operation.
EPCMM3.440 The Expandable Pulse Code Modulation Network card
FB-17217-Ais a time-switch network that provides connections for the
communications paths. The EPCMN contains five separate 256
x 
&bit RAM memories: Control A Memory, Control B Memory,
Information Memory, Pad Memory, and Interconnect Memory.
@ Informat;.sn memory temporarily stores voice, data, and tone
PCM samples until a time switch is made.
@ Control memory temporarily store time slot interchange data,
used to address the information memory to initiate the time slot
interchange.
* Pad memory controls the dB level of attenuation applied to the
PCM output from the time-switch network, determines whether
information memory is to be enabled during this time slot, and
also controls speaker B memory used in a three-way
conversation.
s-44
8237SVR 5210 
						

							TL-130500-1001iNCl&3.4.11 The Synchronizable Intermediate Network Clock
FB-20922-A
card (Figure 3.5) provides the basic timing pulses to the system
network and PCM associated circuitry. The INCKS card permits
the system to communicate over 
Tl trunks. In this case, the
system is slaved to the far end of the span. The INCKS card
also contains the network time slot counter.
The INCKS card receives control inputs from, and outputs clock
pulses to, the EPCMN card.
USE CABLE
CONNECTOR0 ONLY FOR 
ySITHIS CONTROL
HAS NOFUNCTION IN THIS
SVRCRYSTAL
ADJUSTMENT
ACCESS POINTFB-20922-A
ADV SYNC
Figure 3.5INCKS Card Handle View
FB-20922-A
NETWORK CLOCK
CARD HANDLEYELLOW
INDICATORLAMPS
SVR 5210
8/‘87 
						

							TL-130500-1001
INCK
FB-20771 -lA3.4.12 The Intermediate Network Clock card provides all the
functions of the INCKS card, except that Tl’ synchronization is not
possible. This card is used if no Tl functions are used in the
system.
NOTE: Use FB-20922 network clock when network timing is
derived from a 
Tl span (slave operation).
PCMFSFB-17189-A
PCMIFB-17187-A
S-463.4.13 Each 48 channels in the system requires one Pulse Code
Modulation Frame Synchronization card. The PCMFS provides
frame synchronization for the PCM line and trunk cards.
Each PCMFS card receives hardware 
IDS from its respective
CHM85 card and decodes each hardware ID into a discrete
circuit selection, enabling the transfer of PCM to/from that circuit.
l PCMFS in 
X/O5 provides crcuit selection for groups 4 and 5.
l PCMFS in X/O6 provides circuit selection for groups 6 and 7.
l PCMFS in Y/l 6 provides circuit selection for groups 0 and 
1.NOTE: Card location in slot 
X/O6 is required when using group
D.One PCMFS card is located in file Y. This card accommodates
the 48 channels available in the file. In file X, groups C and D
each supply 48 channels: therefore if both groups are in use, two
cards are required.
3.4.14 The Pulse Code Modulation Interface card performs
serial-to-parallel and parallel-to-serial conversion of system
PCM signals.
An 8-bit parallel PCM signal from the time-switch is converted
to a serial PCM signal (24 channels in a 
125-microsecondframe) for transmission to digital line cards. The card also
; recesses signals in the reverse direction. The PCMI contains
two complete converter circuits which can handle a group of 24
channels each.
l 
PCMI in X/O7 performs the conversion processes for groups 4
and 5.
0 PCMI in X/O8 performs the conversion processes for groups 6
and 7.
l 
PCMI in Y/17 performs the conversion processes for groups 0
and 1.
NOTE: The card located in slot 07 is required only when using
Group D.
8/87SVR 5210 
						

							PCMTS
FB-20974-A
FD-1070-AY(full height)Hard Disk Assembly
FD-1070-BD
(half height)FD-1070-BA
Floppy Disk Assembly
SVR 5210TL-130500-1001
3.4.15 The Pulse Code Modulation Tone Source card stores
samples of the various system tones within a ROM (Read-Only
Memory). Tones read from ROM are transferred to the
information memories for use throughout the system. This
provides the dial tone, 
ringback tone, and other alerting tones
used in the system.
The PCMTS receives control inputs from the Network Clock
INCKS or INCK card. The PCM tone sources are stored in ROM
on the PCMTS and, when selected, are applied as data inputs to
information memory on the EPCMN card.
3.4.16 Location: File D, Slots 16-25. The hard disk assembly
consists of a 
S-1:4 inch, 10 megabyte rigid disk that utilizes
Winchester technology, a disk drive controller card, and the disk
mount and associated cable assemblies. The hard disk
assembly contains loader, generic, and data base software. The
software and data base on this disk are loaded into the CPU via
the FMSD card during system initialization and reload
procedures. PD-200 software and data base are loaded into
the PD-200 devices via the FMSD card and the ADMP card
during PD-200 initialization/reload procedures.
3.4.17 Provides the same function as the FD-1070-AY hard
disk assembly.
3.4.18 Location: File D, Slots 26-31. This 
5-l/4 inch, l-megabyte floppy disk assembly is used to SYSGEN the hard disk
during startup. It also provides back-up for the system.
81’87s-47 
						

							TL-130500-1001Digital Trunking3.5 This paragraph provides information about PCBs that are
Printed Circuitinstalled within the Tl span digital trunk preferred location.
BoardsIn this system, only one Tl span, which has a maximum of 24
channels, can be installed. Only file X can be used for this type
of configuration and only certain slots within that file can be used
by these cards. Not all 
Tl span cards require two card slots.
Card slots C6, 
C5, and C4 may be used even if a Tl span is
implemented. However, 4 channels are lost for every 
Tl span
placed.Each card used for a 
Tl span requires two slots and is
referred to as a double height card. Figure 3.6 shows the cards
used by the 
Tl span. Table 3.2 lists the dedicated card slots
used for the 
Tl span.
.__.-
I-PCMUS GROUP C
FILE A
I
- GROUP 4 -1  GROUPh--F-COMMON
- CONTROL __fFILE 
B
I-PCMUS GROUP C-I
EXP;mgIOI
(X)
Figure 3.6Universal PC5 Card Slots Used By A Tl Span
S-488187SVR 5210 
						

							TL-4 30500-l 901Table 3.2 
Tl Span Cards
Card Number Mnemonic and NameCard SlotFB-15278-A, FDC, Frame Detector Card
iX/l0iFB-15280-A, LCM, Line Compensator Card1 x/12
/  FB-17277-A or FB-15277-1, SIL, Span Interface Card
Ixi14II  FB-20718-l A, 
Tl S, 11 -Type Supervisory Card
IX/16(  FB-17192-A, 
Tl B2, Tl Buffer CardXl18SVR 5210
FDC3.51 The Frame Detector card is required for the Tl span and
FB-15278-Aprovides the following functions:
* Monitors for errors in framing synchronization patterns
e Generates a framing alarm signal to the Tl-Type Supervisory
card when three or more bit-pattern errors are found out of
five incoming synchronization bits examined
l Signals the span interface when a new frame of voice samples
is to arrive
l Signals the arrival of bit 2 (the second most important bit) to
the Span Interface card
o Generates the supervisory frame signal that decodes channel
A and B signaling
LCM3.5.2 The Line Compensator card is required for the Tl span.
FB-15280-AThe LCM provides buffering to compensate for propagation
delays due to temperature 
ch :nges over the span. The card can
store two PCM frames that support the compensation process.
The LCM card receives a serial unipolar bit stream from the SIL
(Span Interface cardj. This stream is converted to an 8-bit
voice sample that is forwarded to the Tl-Type Buffer card in
parallel format.
SiL3.5.3 The Span Interface card (Figure 3.7) is required for the 11.FB-17277-Aspan. The SIL receives the incoming bipolar signai and converts
FB-15277-Git to a 
unipolal bit stream which is then sent to the LCM. The SIL
also works in reverse to prepare a bipolar signal for transmission
over the 
Tl span. A strapping field is provided on the card for
application configuration at installation (see TL-130200-1001).
The SIL provides the looping ability to test the framing
synchronization of the digital cards.
8187s-49 
						

							TL-130500-1001
NOTE: To synchronize the PABX digital network timing to theTl -span timing, use FB-15277-l.
s-50USE CABLE
CONNECTOR 0 
-ONLY FOR S I
SINX 0
SINX 1
F&l 5277-IASPAN INTERFACE
CARD HANDLE
Figure 3.7SIL Card Handle View
TlS3.5.4 The Tl-Type Supervisory card is required for the Tl
FB-20718-1Aspan. It provides a supervisory signal interface between the
system and the 
Tl span. The buffers on the TlS card retain the
status of sense and control points.
The 
TlS card has a program board which can be strapped to
decode FX trunk signals or E&M trunk signals. Strapping is also
provided to change from D2 to D3 signaling formats, as well as to
provide a variable framing alarm delay time. Strapping option
procedures are described in TL-130300-1001.
The 
TlS card handle, shown in Figure 3.8, contains the following
lamps and switches:
l Local alarm (LOC) lamp 
tha. lights when the framing of the
incoming bipolar signal is lost (indicating a misframe: loss of
framing synchronization).
8187SVR 5270 
						

							SW 5210TL-130500-1001
l Remote alarm (REM) lamp that lights when the second bit of
an incoming bipolar stream is inhibited for 1.32 to 1.44
seconds.
l System alarm (SYS) lamp that lights when any alarm condition
exists, including when the system is fully frame-synchronized
but in a loop mode.
l Remote power failure alarm (RPF) lamp that lights when a
power failure occurs in the office-terminating shelf.
l Alarm cutoff (ACC) lamp that lights when the alarm cutoff
switch and the loop test switch are activated.
* Two-position alarm cutoff (ACO) s,witch; UP is the activated
position.
9 Loop switch (LP) lamp that indicates when the loop test and
alarm cutoff switches are activated.
l Two-position loop (LPT) switch that must be activated along
with the alarm cutoff switch to start the loop test, UP is the
activated position.
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							TL-130500-1001
RED
INDICATORLAMPSFB-2071 B-A
LOC
IOREM0
SYS0
RPF
,O
AC00
AC0
9
LP
ON
LPTRED
/INDICATORLAMP
FB-20718-1ATl-TYPE
SUPERVISORY
CARD HANDLE
L
Figure 3.8
TlS Card Handle View
TlB23.55 The Tl Buffer card is required for the Tl span. It provides
FB-17192-Aa buffer between the incoming PCM data from the Line
Compensator card and the digital time-switch network in the
system. 
It also buffers the outgoing PCM data from the digital
time-switch network to the Span Interface card. It will
synchronize and align the 24 PCM channels between the digital
network and the Tl digital trunk interface.
S-528187SVR 5210