NEC Neax 2400 Imx Circuit Card Manual

							CHAPTER 3 ND-70182 (E)
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Revision 4.0
PH-CK17-A
Phase Lock Oscillator
4. Lamp Indications
Lamp indications for this circuit card are shown in the table below:
Note:This lamp is effective when this card is mounted in TSWM0 of the IMX-U system.
LAMP NAME COLOR STATE
OPE Green Remains lit while this circuit card is in active state.
MJ RedLights when the following MJ fault has occurred: 
All of the clock supply routes have failed when the system operates as the clock 
subordinate office
32.768 MHz output clock failure (including CLK card)
8 KHz output clock failure (including CLK card)
Input Frame Pulse (FP) failure (FP is supplied by the SYNC card) 
Internal OSC (±5 ppm deviation) have failed when the system operates as the 
clock source office
MN RedLights when the following MN fault has occurred: 
One or more (but not all) DTI/DCS clock supply routes have failed
Drifting failure 
Internal OSC (±5 ppm deviation) failure
SYNC Green Remains lit while the system is synchronized with the network.
ICK Green Lights when the internal oscillator is operating normally.
CKPKG
NoteGreen Lights when the CLK card in TSWM1 is in normal operation.
ALM0
NoteRed Lights when clock failure has occurred in the CLK card.
ALM1
NoteRed Lights when FH failure has occurred in the CLK card.
PALM Red Remains lit when the On-Board Power Supply is abnormal. 
						

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PH-CK17-A
Phase Lock Oscillator
5. Switch Settings
Standard settings for switches on this circuit card are shown in the table below.
Note 1:When this card is used in the 4-IMG or ISWM of the IMX-U system, specify the clock source (DCS or DTI)
according to the clock network configuration for the office.
Note 2:This standard setting is applicable when this card is mounted in TSWM0 of the IMX-U system.
SWITCH 
NAMESETTINGSTANDARD 
SETTINGMEANING
MBUP Circuit card Make-busy.
DOWN×Circuit card Make-busy cancel.
SW03 1 - F 1 Fixed to “1.”
SWITCH 
NAMESWITCH
NO.SETTINGSTANDARD 
SETTINGMEANING
SW01
Note 11ON
×    Note 1Clock subordinate office.
OFF Clock source office.
2ON
×    Note 1Digital Clock Supply route zero (DCS 0) is used.
OFF Digital Clock Supply route zero (DCS 0) is not used.
3ON
×    Note 1Digital Clock Supply route one (DCS 1) is used.
OFF Digital Clock Supply route one (DCS 1) is not used.
4ON8 KHz of Frame Head signals are extracted from the DCS 
signals (which is composed of 64 KHz + 8 KHz).
OFF
×    Note 18 KHz of Frame Head signals are not extracted from the DCS 
signals (which is composed of 64 KHz + 8 KHz).
5ONWhen clock source failure has occurred in all supply routes, the 
PLO outputs the original clock of the internal oscillator.
OFF× When clock source failure has occurred in all supply routes, the 
PLO continues outputting the current phase clock.
6ON
×    Note 1This circuit card is associated with SYNC (PA-CK11) card.
OFF This circuit card is not associated with SYNC (PA-CK11) card.
7ON A-law CODEC is used for Music-On-Hold.
OFF×µ-law CODEC is used for Music-On-Hold.
8 OFF ×Fixed OFF (Not used). 
						

							CHAPTER 3 ND-70182 (E)
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Revision 4.0
PH-CK17-A
Phase Lock Oscillator
Note:
When this card is mounted in TSWM0 of the IMX-U system, DCS clock from the ISW is used. The DTI clock
can also be used as an alternate clock supply route in case of DCS clock failure.
SWITCH 
NAMESWITCH
NO.SETTINGSTANDARD 
SETTINGMEANING
SW02
Note1ON DIU 0 is used as the DTI clock supply route zero.
OFF DIU 0 is not used.
2ON DIU 1 is used as the DTI clock supply route one.
OFF DIU 1 is not used.
3ON DIU 2 is used as the DTI clock supply route two.
OFF DIU 2 is not used.
4ON DIU 3 is used as the DTI clock supply route three.
OFF DIU 3 is not used.
5ON×1.5 M clock for DIU 0.
OFF 2 M clock for DIU 0.
6ON×1.5 M clock for DIU 1.
OFF 2 M clock for DIU 1.
7ON×1.5 M clock for DIU 2.
OFF 2 M clock for DIU 2.
8ON×1.5 M clock for DIU 3.
OFF 2 M clock for DIU 3.
SW101ON  External hold tone source is used via FM lead.
OFF×MUSIC ROM is used as the hold tone.
2ON CLK card is not used.
OFF×CLK card is used. 
						

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PH-CK17-A
Phase Lock Oscillator
SWITCH 
NAMESWITCH
NO.SETTINGSTANDARD 
SETTINGMEANING
SW111
2
3
4
SW121
2
3
4ON Not used
OFF×Not used
5
MUSIC (CH1) selection. The music varies depending on the melody IC located on this circuit 
card. 6
7
8ON Not used
OFF×Not used
SW11-1 SW11-2Impedance of the External 
Music Source 0 (FM 0)
OFF OFF 600 Ω
ON OFF 8.2 Ω
OFF ON 47K Ω
SW11-3 SW11-4Impedance of the External 
Music Source 1 (FM 1)
OFF OFF 600 Ω
ON OFF 8.2 Ω
OFF ON 47K Ω
SW12-1 SW12-2 SW12-3 MUSIC
OFF OFF OFF Für Elise
ON OFF OFF Maiden’s prayer
Not Used ON OFF Buzzer
Not Used OFF ON Chime 
						

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PH-CK17-A
Phase Lock Oscillator
6. External Interface
PLO input leads appear on the LT connectors labeled EXCLK0 and EXCLK1
PLO mounting slots
The PLO card is mounted in slots 21 and 23 of TSWM.
LT cable connectors
Connect the LT cables to the connectors labeled EXCLK0 and EXCLK1 on the TSWM backplane.
Figure 3-26   PLO Pin Assignments for Receiving Clock (4 IMG System) (1/2) 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
EXCLK0EXCLK1
PLO
PLO
TSW Front View
TSWM
EXCLK0EXCLK1
TSWMBackplane 
						

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PH-CK17-A
Phase Lock Oscillator
EXCLK0/EXCLK1 connector Pin Assignment
Pins are assigned as follows on the EXCLK0/EXCLK1 connectors. When the clock is distributed from a
digital interface, use one pair of DIUxxx in one of the 4 inputs. (There are a maximum of 4 inputs.) DIU
leads have the following precedence: DIU0xx (high) 
➝ DIU3xx (low).
Figure 3-26   PLO Pin Assignments for Receiving Clock (4 IMG) (2/2)
PLO input leads appear on the LT connectors labeled EXCLK0 and EXCLK1.
PLO mounting slots
The PLO card is mounted in Slots 09 and 13 of ISWM.
34PH ISWM EXCLK CA-A
34PH ISWM EXCLK CA-A
REAR VIEW
EXCLK0EXCLK1TSWM
MDF
Installation Cable To Digital Interface and/or DCS
34PH ISWM EXCLK CA-A Cable Lead Location
26
27
28
29
30
31
32
33
34
35
36
37
381
2
3
4
5
6
7
8
9
10
11
12
13 FM1
FM0
DIU3B
DIU2B
DIU1B
DIU0B
DCSB
SYN1B
SYN0BE
E
DIU3A
DIU2A
DIU1A
DIU0A
DCSA
SYN1A
SYN0A
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 23EXCLK0EXCLK1
PLO
PLO
Front View
ISWM 
						

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PH-CK17-A
Phase Lock Oscillator
LT cable connectors
Connect LT cables to the connectors labeled EXCLK0 and EXCLK! on the ISWM backplane.
Figure 3-27   PLO Pin Assignment for Receiving Clock (ISW) (1/2)
EXCLK0/EXCLK1 connector Pin Assignment
Pins are assigned as follows on the EXCLK0/EXCLK1 connectors. When the clock is distributed from a
digital interface, use one pair of DIUxxx in one of the 4 inputs. (There are a maximum of 4 inputs.) DIU
leads have the following precedence: DIU0xx (high) 
➝ DIU3xx (low).
Figure 3-27   PLO Pin Assignment for Receiving Clock (ISW) (2/2)
EXCLK1EXCLK0
Backplane
ISWM
MDF
To Digital Interface and/or DCSInstallation Cable
ISWMEXCLK0
(Slot No.09) EXCLK1
(Slot No.13)
34PH ISWM EXCLK CA-A
34PH ISWM EXCLK CA-A
Rear View26
27
28
29
30
31
32
33
34
35
36
37
381
2
3
4
5
6
7
8
9
10
11
12
13 FM1
FM0
DIU3B
DIU2B
DIU1B
DIU0B
DCSB
SYN1B
SYN0BE
E
DIU3A
DIU2A
DIU1A
DIU0A
DCSA
SYN1A
SYN0A 
						

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PH-CK17-A
Phase Lock Oscillator
Cable Connection Diagram
Provide the following wiring at the MDF. The following connection diagram shows an example of a system
that has the PLO cards in dual configuration. Figure 3-28 is a cable connection diagram (ISW) for accepting
synchronization clocks from an external high-stability oscillator.
Figure 3-28   Cable Connection (ISW) for Accepting Synchronization Clocks from an External Oscillator
MDF ISW
External
High-Stability
Oscillator #1
CLK
External
High-Stability
Oscillator #0
CLK PCM Cable(IP) PCM Cable(IP)
DCSA
DCSB LT Connector Cable
EXCLK1
DCSB
DCSA LT Connector Cable
EXCLK0
EXCLK1PLO#1
EXCLK0PLO#0
BASEUmaximum 400 meters (1320 feet)   (24 AWG) 
						

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PH-CK17-A
Phase Lock Oscillator
This figure shows an example of distributing clock from a digital interface in LN. This example assumes that
the Digital Trunk POUT leads are used as the first clock distribution route.
Figure 3-29   Cable Connection Diagram (ISW) for Receiving Clock from Digital Interface
MDF
ISWLN
PCM
Carrier
Equipment
DSU
CLK PCM Cable (2P)
to other node
Installation CableInstallation Cable maximum 100
meters (330 feet)
            (24AWG)Installation Cable
RA
RB
TA
TB
POUTA
POUTB
DIU0A0
DIU0B0
DIU1A0
DIU1B0
DIU2A0
DIU2B0
DIU3A0
DIU3B0
DIU0A1
DIU0B1
DIU1A1
DIU1B1
DIU2A1
DIU2B1
DIU3A1
DIU3B1 EXCLK0PLO#0
LT Connector
Digital
Interface
EXCLK1PLO#1maximum 200 meters (660 feet)   (24AWG)
Note 1:
Note 1
Note 2
PLO has a maximum 4 inputs. DIU0xx leads are used for the 1st clock distribution routes. DIU3xx 
leads are used for the 4th. The first input has the highest priority.
Note 2:The connection is required for a dual PLO system. 
						

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PH-CK17-A
Phase Lock Oscillator
Figure 3-30   LT Connector Lead Location of PLO (ISW-LN0)
CLK00
(Slot No.08) CLK10
(Slot No.12)
TSWM1
TSWM0 ISWM
Installation Cable DIU Connection Note
MDF
To Digital Interface 
EXCLK0
(Slot No.21)
PLO CLOCK0
(Slot No.21)
EXCLK1
(Slot No.23)
PLO CLOCK1
(Slot No.23)PLO CLOCK0
(Slot No.21)PLO CLOCK1
(Slot No.23)
ISW-LN PLO CA-A
PLO-CLK CA-A DCS Connection
Note:For DIU connection route diagram, see the figure on the next page.
261 LEAD
NAMELEAD
NAME
272
283 PIN
No. PIN
No.
294
305 FM1
FM0
316
327
338
349
3510E
DIU 3B
DIU 2BDIU 3A
DIU 2AE
DIU 1B
DIU 1A
DIU 0B
DIU 0A