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NEC Neax 2400 Imx Circuit Card Manual

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    							CHAPTER 2 ND-70182 (E)
    Page 106
    Revision 4.0
    PH-SW10
    Time Division Switch
    2. Mounting Location/Condition
    This circuit card is mounted in PIM0 in the slot shown below.
    3. Face Layout of Lamps, Switches, and Connectors
    The face layout of lamps, switches and connectors is shown below.
    Figure 2-50   Face Layout of PH-SW10 (TSW) 00 01 02 03 04 05 06 07 08 09 10 11
    1213 14 15 16 17 18 19 20 21 22 23
    Mounting ModulePIM
    PIM0 
    TSW #1
    TSW #0
    1   2  3  4  5  6  7  8 
    SW11
    TSWACT
    MUXACT
    PLOACT
    MB
    TSWMBR
    PLOMB
    M3SY
    M2SY
    M1SY
    M0SY
    CFT
    SYNC
    ICK
    ECK
    SW03
    SW04
    MUX3
    MUX2
    MUX1PMCA
    PMJ
    PMN
    SW12 
    						
    							ND-70182 (E) CHAPTER 2
    Page 107
    Revision 4.0
    PH-SW10
    Time Division Switch
    4. Lamp Indications
    Lamp indications for this circuit card are shown in the table below.
    LAMP NAME COLOR STATE
    TSWACTGreen Remains lit while the TSW block is in ACT state.
    Red Remains lit while the TSW block is in Make-busy state.
    Off Remains off while the TSW block is ST-BY side.
    MUXACT Green Remains lit while MUX block is in ACT state.
    PLOACT Green Remains lit while PLO block is in ACT state.
    M3SY Green Lights when MUX #3 synchronization has been established.
    M2SY Green Lights when MUX #2 synchronization has been established.
    M1SY Green Lights when MUX #1 synchronization has been established.
    M0SY Green Lights when MUX #0 synchronization has been established.
    PMCA Red Lights when the PM/PCM bus clock FH failure has occurred.
    CFT Green Lights when the CFT circuit is valid.
    PMJ RedLights when the following MJ fault has occurred:
    All of the clock supply routes have failed when the system operates as the clock 
    subordinate office
    32.768 MHz output clock failure
    8 KHz output FH failure
    5 msec × “n” output FH failure
    Input Frame Pulse (FP) failure (FP is supplied by the SYNC card)
    Both internal OSC (±5 ppm deviation) and high-precision clock signals (±0.3 ppm 
    deviation) have failed when the system operates as the clock source office
    PMN YellowLights when the following MN fault has occurred:
    One or more (but not all) DTI/DCS clock supply routes have failed
    Drifting failure
    Internal OSC (±5 ppm) failure
    High-precision clock signals (±0.3 ppm) failure 
    						
    							CHAPTER 2 ND-70182 (E)
    Page 108
    Revision 4.0
    PH-SW10
    Time Division Switch
    5. Switch Settings
    Standard settings for switches on this circuit card are shown in the table below.
    SYNCGreen Remains lit while the system is synchronized with the network.
    OFFRemains off when any of the following have occurred.
    DCS clock failure when receiving the clock signals from the DCS.
    DTI clock failure when receiving the clock signals from the DTI.
    Drifting failure
    ICK GreenLights when the TSW (PA-SW10) internal oscillator is operating normally.
    Note:The ICK LED will illuminate even when the internal PLO circuit is
    operational.
    ECK GreenLights when the high-precision clock signals are received from OSC circuit card (PA-
    CK14). 
    Note:The ICK LED will not illuminate when the PA-CK14 is operational.
    SWITCH 
    NAMESETTINGSTANDARD 
    SETTINGMEANING
    MBUP Circuit card Make-busy.
    DOWN×Circuit card Make-busy cancel.
    TSWMBRUP TSW Make-busy request.
    DOWN×TSW Make-busy request cancel.
    PLOMBRUP PLO Make-busy request.
    DOWN×PLO Make-busy request cancel.
    SW12 1-F 1 Fixed to “1.” LAMP NAME COLOR STATE 
    						
    							ND-70182 (E) CHAPTER 2
    Page 109
    Revision 4.0
    PH-SW10
    Time Division Switch
    Note:
    When MUX card mode (SW03-4 ON), only MUX and CFT functions are valid. MUX 1 is used for a con-
    nection to TSW (Don’t use MUX 2, 3). The LED of MUXACT, M0SY, CFT, and PMCA are valid, other LED
    is not lit. In the case of this mode, only SW03 is valid.
    SWITCH 
    NAMESWITCH
    NOSETTINGSTANDARD 
    SETTINGMEANING
    SW031ON 3-Party Conference Trunk (CFT) is valid.
    OFF 3-Party Conference Trunk (CFT) is invalid.
    2ON Setting of A-law in the CFT function block.
    OFF×Setting of µ-law in the CFT function block.
    3OFF×Fixed.
    4ONOnly MUX function is valid (If this card is mounted in PIM 
    1/2/3).Note 
    OFF×TSW/INT/PLO/MUX are valid (When this card is mounted 
    in PIM 0).
    SW041ON DIU 0 is used as the DTI clock supply route zero.
    OFF DIU 0 is not used.
    2ON DIU 1 is used as the DTI clock supply route one.
    OFF DIU 1 is not used.
    3ON DIU 2 is used as the DTI clock supply route two.
    OFF DIU 2 is not used.
    4ON DIU 3 is used as the DTI clock supply route three.
    OFF DIU 3 is not used.
    5ON×1.5 M clock for DIU 0
    OFF 2 M clock for DIU 0
    6ON×1.5 M clock for DIU 1
    OFF 2 M clock for DIU 1
    7ON×1.5 M clock for DIU 2
    OFF 2 M clock for DIU 2
    8ON×1.5 M clock for DIU 3
    OFF 2 M clock for DIU 3 
    						
    							CHAPTER 2 ND-70182 (E)
    Page 110
    Revision 4.0
    PH-SW10
    Time Division Switch
    SWITCH 
    NAMESWITCH 
    NO.SETTINGSTANDARD 
    SETTINGMEANING
    SW111ON PLO operates as the clock subordinate office.
    OFF PLO operates as the clock source office.
    2ON Digital Clock Supply route zero (DCS 0) is used.
    OFF Digital Clock Supply route zero (DCS 0) is not used.
    3ON Digital Clock Supply route one (DCS 1)  is used.
    OFF Digital Clock Supply route one (DCS 1) is not used.
    4ON8 KHz of Frame Head signals are not extracted from the DCS 
    signals (which is composed of  64KHz + 8KHz).
    OFF8 KHz of Frame Head signals are extracted from the DCS 
    signals (which is composed of  64KHz + 8KHz).
    5ONWhen clock source failure has occurred in all supply routes, 
    the PLO outputs the original clock of the internal oscillator. 
    OFFWhen clock source failure has occurred in all supply routes, 
    the PLO continues outputting the current phase clock.
    6ON This card is associated with SYNC (PA-CK16 WCS) card.
    OFFThis card is not associated with SYNC (PA-CK16 WCS) 
    card.
    7ON (The last byte data of the DTG ROM is “FE”)
    OFF×(The last byte data of the DTG ROM is “FF”)
    8OFF×Not used 
    						
    							ND-70182 (E) CHAPTER 2
    Page 111
    Revision 4.0
    PH-SW10
    Time Division Switch
    6. External Interface
    When this circuit card is used in “clock subordinate office”, clock signals from DTI, CCT, PRT must be
    extracted. See Figure 2-52 for more information. When this circuit card is used in “clock source office”
    cable connections are not necessary.
    Figure 2-51   PLO Connector Leads Location
    2627
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    501
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25DCSB0
    DIU0B0
    DIU1B0
    DIU2B0
    DIU3B0
    SYN0B0
    SYN1B0
    DCSB1
    DIU0B1
    DIU1B1
    DIU2B1
    DIU3B1
    SYN0B1
    SYN1B1DCSA0
    DIU0A0
    DIU1A0
    DIU2A0
    DIU3A0
    SYN0A0
    SYN1A0
    DCSA1
    DIU0A1
    DIU1A1
    DIU2A1
    DIU3A1
    SYN0A1
    SYN1A1Mounting ModulePIM 
    						
    							CHAPTER 2 ND-70182 (E)
    Page 112
    Revision 4.0
    PH-SW10
    Time Division Switch
    Figure 2-52   Connecting Route Diagram
    DCS
    TSW #1 TSW #0/PRT CCT/DTI CCT/DTI
    /PRT CCT/DTI
    /PRT CCT/DTI
    /PRTPOUT A
    POUT B
    POUT A
    POUT B
    POUT A
    POUT B
    POUT A
    POUT B
    DCSA0
    DCSB0
    DIU0A0
    DIU0B0
    DIU1A0
    DIU1B0
    DIU2A0
    DIU2B0
    DIU3A0
    DCSA1
    DCSB1
    DIU0A1
    DIU0B1
    DIU1A1
    DIU1B1
    DIU2A1
    DIU2B1
    DIU3A1
    DIU3B1 PBX MDF
    Note: The following circuit cards have Clock Output leads for a PLO card: CCT (PA-24CCTA, PA30CCTB),
    DTI (PA-24DTR, PA-30DTS), and PRT (A-24PRT, PA-PRTC).
    DIU3B0 
    						
    							ND-70182 (E) CHAPTER 2
    Page 113
    Revision 4.0
    PH-SW10
    Time Division Switch
    The front cable connections are shown in Figure 2-53.
    Figure 2-53   Front Cable Connections for PH-SW10
    TDSW
    #0
    MUX
    #0
    MUX
    #0MUX
    #1
    MUX
    #1
    MUX
    #1MUX
    #0
    TDSW
    #1
    MT24 TDSW CA-180
    MT24 TDSW CA-140
    MT24 TDSW CA-90
    PIM 3
    PIM 2
    PIM 1
    PIM 0 
    						
    							CHAPTER 2 ND-70182 (E)
    Page 114
    Revision 4.0
    PH-SW10
    Time Division Switch
    7. Switch Setting Sheet
    SWITCH NAME SWITCH SHAPE REMARKS
    MB
    TSWMBR
    PLOMB
    SW03
    SW04
    SW11
    SW12
    ON
    ON
    ON
    1234ON
    1234ON5678
    1234ON5678
    1 
    						
    							ND-70182 (E) CHAPTER 2
    Page 115
    Revision 4.0
    PH-SW12
    Time Division Switch
    PH-SW12
    Time Division Switch
    1. General Function
    This circuit card provides the Time Division Switch (TSW) and INT function for the system. Each TSW
    card is capable of 8192 × 2048 Time Slot (TS) switching for an Interface Module Group (IMG). Four cards
    allow 8192 × 8192 TS switching for the 4 IMG configuration.
    The INT is an intermediate circuit of the CPR which controls and administrates the Port Microprocessor
    (PM) for line/trunk circuit cards. 
    Figure 2-54   TSW Configuration
    TSW
    (8Kx2K)
    TSW
    (8Kx2K)
    TSW
    (8Kx2K)
    TSW
    (8Kx2K)IMG0 IMG0
    IMG1 IMG1
    IMG2 IMG2
    IMG3 IMG3
    [TSW configuration]
    [INT configuration]
    CPU1(LP) ISAGT1 GT1
    CPU0(LP) ISAGT0 GT0
    TSW1
    (INT)
    TSW0
    (INT)
    MUX01
    MUX30
    MUX31
    MUX00LC/TRK(PM)
    LC/TRK(PM) ISA BUS I/O BUS
    ISA BUS I/O BUS System #1
    System #0ACT
    STBYSTBY
    STBY STBY
    ACT ACTACT
    PM BUS PM BUS 
    						
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