NEC Neax 2400 Ipx Wireless System Manual
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![Page 98
NDA-24301 CHAPTER 3
Page 81
Revision 1.0
[Firmware: SW-360]
Note 1:
PAD control is shown below.
SWITCH NAMESWITCH
NUMBERSWITCH
SETTINGSTANDARD
SETTINGMEANING
SW12
(DIP Switch)
1~8
ON
12
3456 78
Connection with C.O. Note
Connection with a station Note
SWITCH 1 SWITCH 2 SWITCH 3 PAD VALUE
OFF OFF OFF Not used
ON OFF OFF Not used
OFF ON OFF PAD 1=3 dB
ON ON OFF PAD 1=0 dB
OFF OFF ON PAD 1=–3 dB
ON OFF ON PAD 1=–5 dB
(Standard setting)
OFF ON ON PAD 1=–7 dB
ON ON ON PAD 1=–10 dB
SWITCH 4 PAD VALUE
ON PAD...](http://img.usermanuals.tech/thumb/54/84277/w64_nec-neax2400-ipx-wireless-system-manual_d-97.png "Page 98
NDA-24301 CHAPTER 3
Page 81
Revision 1.0
[Firmware: SW-360]
Note 1:
PAD control is shown below.
SWITCH NAMESWITCH
NUMBERSWITCH
SETTINGSTANDARD
SETTINGMEANING
SW12
(DIP Switch)
1~8
ON
12
3456 78
Connection with C.O. Note
Connection with a station Note
SWITCH 1 SWITCH 2 SWITCH 3 PAD VALUE
OFF OFF OFF Not used
ON OFF OFF Not used
OFF ON OFF PAD 1=3 dB
ON ON OFF PAD 1=0 dB
OFF OFF ON PAD 1=–3 dB
ON OFF ON PAD 1=–5 dB
(Standard setting)
OFF ON ON PAD 1=–7 dB
ON ON ON PAD 1=–10 dB
SWITCH 4 PAD VALUE
ON PAD...")
![Page 103
CHAPTER 3 NDA-24301
Pag e 8 6
Revision 1.0
PA-CK16 [SYNC] Synchronous Signal Transmission Circuit for CS/ZT
1. General Function
This circuit card is designed to realize 5 ms synchronization between CSINTs (Clock Source Office and
Subordinate Office) in conjunction with the PLO card. Details are shown in Figure 3-17.
Figure 3-17 Location of Card in the System
Detection
MD F
Clock Source OfficeClock Subordinate Office
TSW MUXPA-CK16
PLO
PLO TSW MUX
PA-CK16
Loopback signal
5 ms signal...](http://img.usermanuals.tech/thumb/54/84277/w64_nec-neax2400-ipx-wireless-system-manual_d-102.png "Page 103
CHAPTER 3 NDA-24301
Pag e 8 6
Revision 1.0
PA-CK16 [SYNC] Synchronous Signal Transmission Circuit for CS/ZT
1. General Function
This circuit card is designed to realize 5 ms synchronization between CSINTs (Clock Source Office and
Subordinate Office) in conjunction with the PLO card. Details are shown in Figure 3-17.
Figure 3-17 Location of Card in the System
Detection
MD F
Clock Source OfficeClock Subordinate Office
TSW MUXPA-CK16
PLO
PLO TSW MUX
PA-CK16
Loopback signal
5 ms signal...")
![Page 104
NDA-24301 CHAPTER 3
Page 87
Revision 1.0
2. Mounting Location/Condition
The PA-CK16 [SYNC] card can be mounted in any universal slot as shown below.
Note 1: Indicates universal slots for line/trunk circuit cards.
Note 2:Do not accommodate an analog line in the LT connector used by this card.
3. Face Layout of Lamps and Switches
The face layout of lamps and switches is shown in Figure 3-18.
Figure 3-18 Lamp, Key and Connectors: PA-CK16
PIMMounting Module
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15...](http://img.usermanuals.tech/thumb/54/84277/w64_nec-neax2400-ipx-wireless-system-manual_d-103.png "Page 104
NDA-24301 CHAPTER 3
Page 87
Revision 1.0
2. Mounting Location/Condition
The PA-CK16 [SYNC] card can be mounted in any universal slot as shown below.
Note 1: Indicates universal slots for line/trunk circuit cards.
Note 2:Do not accommodate an analog line in the LT connector used by this card.
3. Face Layout of Lamps and Switches
The face layout of lamps and switches is shown in Figure 3-18.
Figure 3-18 Lamp, Key and Connectors: PA-CK16
PIMMounting Module
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15...")
CHAPTER 3 NDA-24301 Pag e 8 4 Revision 1.0 6. External interface Shown in Figure 3-15 are accommodation of the LT connector leads of this circuit card and connecting route diagram. a. When this circuit card is mounted in PIM. Figure 3-15 LT Connector Leads Accommodation of PIM : PA-4CSIF 26272829303132333435363738394041 1234567891011121314151642434445464748 1718192021222349502425 Accommodated in *1 LT0, 2, 4, 6, 8, 10 Connector LT Connector Accommodation 26272829303132333435363738394041 1234567891011121314151642434445464748 1718192021222349502425 Accommodated in *2 LT1, 3, 5, 7, 9,11 Connector 26272829303132333435363738394041 1234567891011121314151642434445464748 1718192021222349502425 Accommodated in *3 LT1, 3, 5, 7, 9, 11 Connector 232221201918171615141312111009080706050403020100 LT6 LT7 LT8 LT9 LT10 LT11LT0 LT1 LT2 LT3 LT4 LT5 23 19 15 22 18 14 21 17 13 20 16 1223 19 15 22 18 14 21 17 13 20 16 12 11 09 07 05 03 01 10 08 06 04 02 00 11 09 07 05 03 01 10 08 06 04 02 00 Group No. Slot No. LT Connector Name PIM 32 ** Highway Block 01324567981011 2* 1* 1* 2* 3* 1* 3* 1* 3* 1* 3* 2* 1* 3* 2* B0 B1 B2 B3A0 A1 A2 A3 2* B0 B1 B2 B3A0 A1 A2 A3 B0 B1 B2 B3A0 A1 A2 A3 PWR PWR
NDA-24301 CHAPTER 3 Page 85 Revision 1.0 Figure 3-16 Connecting Route Diagram MDF PIM NT1 A B CSINTA B
CHAPTER 3 NDA-24301
Pag e 8 6
Revision 1.0
PA-CK16 [SYNC] Synchronous Signal Transmission Circuit for CS/ZT
1. General Function
This circuit card is designed to realize 5 ms synchronization between CSINTs (Clock Source Office and
Subordinate Office) in conjunction with the PLO card. Details are shown in Figure 3-17.
Figure 3-17 Location of Card in the System
Detection
MD F
Clock Source OfficeClock Subordinate Office
TSW MUXPA-CK16
PLO
PLO TSW MUX
PA-CK16
Loopback signal
5 ms signal
ExtractionRetransmission5 ms synchronous signal
CSINT
CSINT
5 ms signal 5 ms signal5 ms signal 5 ms signal
1
2
3
3
4
5
The Clock Source Office side transmits the 5 ms synchronous signal (which synchronize with TSW/MUX)
to the Clock Subordinate Office side.
The Clock Subordinate Office side extracts the 5 ms synchronous signal from transmitted signal.
The Clock Subordinate Office side transmits the extracted 5 ms synchronous signal to PLO, at that time,
loops back the 5 ms synchronous signal to the Clock Source Office side.
The Clock Source Office side detects a phase difference between looped 5 ms synchronous signal and 5 ms
synchronous signal output from TSW/MUX.
The Clock Source Office side retransmits the revised signal to Clock Subordinate Office.
Note 1:Maximum length of the cable connection between the Clock Source Office and the Clock Subordinate
Office is 6560 ft. (24 awg) [2000 m (0.5φ)].
1
2
3
4
5
Note 1
NDA-24301 CHAPTER 3 Page 87 Revision 1.0 2. Mounting Location/Condition The PA-CK16 [SYNC] card can be mounted in any universal slot as shown below. Note 1: Indicates universal slots for line/trunk circuit cards. Note 2:Do not accommodate an analog line in the LT connector used by this card. 3. Face Layout of Lamps and Switches The face layout of lamps and switches is shown in Figure 3-18. Figure 3-18 Lamp, Key and Connectors: PA-CK16 PIMMounting Module 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 1918 20 21 22 23 SYNC 3 SERR 3 TLOS 3 RLOS 3 SYNC 2 SERR 2 TLOS 2 RLOS 2 SYNC 1 SERR 1 TLOS 1 RLOS 1 SYNC 0 SERR 0 TLOS 0 RLOS 0 MB KEYOPE SW 01 SW 02
CHAPTER 3 NDA-24301 Pag e 8 8 Revision 1.0 4. Lamp Indications The contents of lamp indications on this circuit card are shown in Table 3-2: Note:When the input loopback signal failure occurs in the clock source office, the office suspends output of the slave signal. Table 3-2 PA-CK16 Lamp Indications Reference LAMP NAME COLOR MEANING OPE Green Remains lit while this circuit card is in normal operation. SYNC 0 Green Lights when the Circuit 0 is synchronized. SERR 0 Red Lights when the Circuit 0 is out of synchronization. TLOS 0 Red Lights when an output slave signal of the Circuit 0 is disconnected. RLOS 0 Red Lights when an input loopback signal of the Circuit 0 is disconnected. Note SYNC 1 Green Lights when the Circuit 1 is synchronized. SERR 1 Red Lights when the Circuit 1 is out of synchronization. TLOS 1 Red Lights when an output slave signal of the Circuit 1 is disconnected. RLOS 1 Red Lights when an input loopback signal of the Circuit 1 is disconnected. Note SYNC 2 Green Lights when this Circuit 2 is synchronized. SERR 2 Red Lights when this Circuit 2 is out of synchronization. TLOS 2 Red Lights when an output slave signal of the Circuit 2 is disconnected. RLOS 2 Red Lights when an input loopback signal of the Circuit 2 is disconnected. Note SYNC 3 Green Lights when the Circuit 3 is synchronized. SERR 3 Red Lights when the Circuit 3 is out of synchronization. TLOS 3 Red Lights when an output slave signal of the Circuit 3 is disconnected. RLOS 3 Red Lights when an input loopback signal of the Circuit 3 is disconnected. Note
NDA-24301 CHAPTER 3 Page 89 Revision 1.0 5. Switch Settings Standard settings of switches on this circuit card are shown in Table 3-3. Table 3-3 Standard Switch Settings SWITCH NAMESWITCH No.SETTINGSTANDARD SETTINGMEANING MBUP Circuit card make busy. DOWNxCircuit card make busy cancel. SW011ON Circuit 0 alarm detection is not used. OFF Circuit 0 alarm detection is used. 2ON Circuit 1 alarm detection is not used. OFF Circuit 1 alarm detection is used. 3ON Circuit 2 alarm detection is not used. OFF Circuit 2 alarm detection is used. 4ON Circuit 3 alarm detection is not used. OFF Circuit 3 alarm detection is used. 5OFF xFixed to OFF. 6 ~ 8 OFF xFixed to OFF. SW021ON When Circuit 0 is used to receive the clock. OFF When Circuit 0 is used to transmit the clock. 2ON When Circuit 1 is used to receive the clock. OFF When Circuit 1 is used to transmit the clock. 3ON When Circuit 2 is used to receive the clock. OFF When Circuit 2 is used to transmit the clock. 4ON When Circuit 3 is used to receive the clock. OFF When Circuit 3 is used to transmit the clock. 5OFF xFixed to OFF. 6OFF xFixed to OFF. 7OFF xFixed to OFF. 8OFF xFixed to OFF.
CHAPTER 3 NDA-24301 Pag e 9 0 Revision 1.0 6. External Interface Figure 3-19 LT Connector Lead Accommodation of PIM: PA-CK16 (1/2) 26272829303132333435363738394041 1234567891011121314151642434445464748 1718192021222349502425 232221201918171615141312111009080706050403020100 LT6 LT7 LT8 LT9 LT10 LT11LT 0 LT 1 LT 2 LT 3 LT 4 LT 5 23 19 15 22 18 14 21 17 13 20 16 1223 19 15 22 18 14 21 17 13 20 16 12 11 09 07 05 03 01 10 08 06 04 02 00 11 09 07 05 03 01 10 08 06 04 02 00 HW11 HW10 HW9 HW8 HW7 HW6 HW5 HW4 HW3 HW2 HW1 HW0 Group No. Slot No. LT Connector PIM Highway BlockLT 1, 3, 5, 7, 9, 11 Connector 26272829303132333435363738394041 1234567891011121314151642434445464748 1718192021222349502425 S5M0B Accommodated in 1 LT 0, 2, 4, 6, 8, 10 Connector S5M0A S5M1A S5M1BAccommodated in 2 LFH0B SFH0BLFH0A SFH0A LFH1A SFH1A LFH1B SFH1B LFH2B SFH2BLFH2A SFH2A LFH3A SFH3A LFH3B SFH3B LFH0B SFH0BLFH0A SFH0A LFH1A SFH1A LFH1B SFH1B LFH2B SFH2BLFH2A SFH2A LFH3A SFH3A LFH3B SFH3BS5M0B S5M0A S5M1A S5M1B 12 1 212 121 212 PIMMounting Module
NDA-24301 CHAPTER 3 Page 91 Revision 1.0 Figure 3-19 LT Connector Lead Accommodation of PIM: PA-CK16 (2/2) 26272829303132333435363738394041 1234567891011121314151642434445464748 1718192021222349502425 26272829303132333435363738394041 1234567891011121314151642434445464748 1718192021222349502425 S5M0B Accommodated in 3 LT 0, 2, 4, 6, 8, 10 Connector S5M0A S5M1A S5M1BLFH0B SFH0BLFH0A SFH0A LFH1A SFH1A LFH1B SFH1B LFH2B SFH2BLFH2A SFH2A LFH3A SFH3A LFH3B SFH3B LT 1, 3, 5, 7, 9, 11 Connector 232221201918171615141312111009080706050403020100 LT6 LT7 LT8 LT9 LT10 LT11LT 0 LT 1 LT 2 LT 3 LT 4 LT 5 23 19 15 22 18 14 21 17 13 20 16 1223 19 15 22 18 14 21 17 13 20 16 12 11 09 07 05 03 01 10 08 06 04 02 00 11 09 07 05 03 01 10 08 06 04 02 00 HW11 HW10 HW9 HW8 HW7 HW6 HW5 HW4 HW3 HW2 HW1 HW0 Group No. Slot No. LT Connector PIM Highway Block 333333 PIMMounting Module
CHAPTER 3 NDA-24301 Pag e 9 2 Revision 1.0 Figure 3-20 Connecting Route Diagram PLO 1 PA-CK16 5 ms signal Clock Source Office PLO 0 PLO 1 PA-CK16 Clock Subordinate Office Note 4SFH0A SFH0B LFH0A LFH0B S5M0A S5M0B S5M1A S5M1B LFH1A LFH1B SFH1A SFH1B LFH2A LFH2B SFH2A SFH2B LFH3A LFH1A LFH1B SFH1A SFH1B LFH2A LFH2B SFH2A SFH2B LFH3A LFH3B SFH3A SFH3BSYN0A SYN0B LFH3B SFH3A SFH3B SYN0A SYN0B Note 1 Note 1 Note 2 MDF LFH0A LFH0B SFH0A SFH0B Max. 2000m (0.5 )φ PLO 0 Note 1:Clock synchronization with more than three nodes is possible. For more details, refer to Figure 3-21. Note 2:The connection is required for a dual PLO system.
NDA-24301 CHAPTER 3 Page 93 Revision 1.0 The PA-CK16 [SYNC (WCS)] has four ports to synchronize with other PBXs. Figure 3-21 shows an example of clock network using PA-CK16. Figure 3-21 Example of Clock Network Using PA-CK16 [SYNC] SYNC (Clock Source Office)SYNC SYNC SYNC SYNC SYNC SYNC SYNC LFH0A, LFH0B, SFH0A, SFH0B LFH3A, LFH3B, SFH3A, SFH3B LFH2A, LFH2B, SFH2A, SFH2B LFH1A, LFH1B, SFH1A, SFH1BLFH1A, LFH1B, SFH1A, SFH1B LFH2A, LFH2B, SFH2A, SFH2B LFH3A, LFH3B, SFH3A, SFH3B Step 1 Step 2 Actual MDF connection, refer to Figure 3-20. Note 1:Clock synchronization with more than three nodes is possible. Note 2:Do not connect to more nodes (There are a maximum of two steps to connect to other SYNCs from the Clock Source Office.) Note 3:SW02-1 ~ SW02-4 SW settings. For more details, refer to Switch Settings. Port which receives the clock (5 ms signal) : ON Port which transmits the clock (5 ms signal) : OFF Note 1 Note 1 Note 1Note 2 Note 2 Note 2