Fujitsu Series 3 Manual

 
7. UART (Async Serial Interface) Registers 
 
[bit 9] TDRE: Transmit data empty flag bit   This flag shows the state of  Transmit Data Register (TDR). 
   If transmit data is written in the TDR, this bit is set to 0 to indicate that the TDR contains valid data. 
When data is loaded to the transmit shift register and  when the transmission is started, this bit is set to 
1 to indicate that the TDR does not have the valid data. 
   If the TDRE bit and SCR:TIE bit are 1,  a transmit interrupt request...

 
7. UART (Async Serial Interface) Registers 
 
7.4.  Extended Communication Control Register (ESCR) 
The Extended Communication Control Register (ESCR) is used to set a transmit/receive data 
length, enable/disable a parity bit, select a parity bit, invert the serial data format and set stop 
bit length selection. 
 bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SSR) FLWEN ESBLINV PEN P L2 L1 L0 
Attribute     R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] FLWEN: Flow control...

 
7. UART (Async Serial Interface) Registers 
 
   In receive operation, only the first bit of the
  stop bit data is detected. 
   Always set this bit when transmission is disabled (SCR:TXE=0). 
 
[bit 5] INV: Inverted serial data format bit  Selects NRZ or inverted  

NRZ for the serial data format. 
Bit Description 
0 NRZ  format 
1 Inverted NRZ format 
 
[bit 4] PEN: Parity enable bit (only functions in operation mode 0)  Sets to add (for transmission) and detect  (for reception) a parity bit or...

 
7. UART (Async Serial Interface) Registers 
 
[bit 2:0] L2, L1, L0: Data length select bit These bits set a length of transmit/receive data. 
- If set to 0b000, the data length is set to eight bits. 
- If set to 0b001, the data length is set to five bits. 
- If set to 0b010, the data length is set to six bits. 
- If set to 0b011, the data length is set to seven bits. 
- If set to 0b100, the data length is set to nine bits. 
Bit 2  Bit 1Bit 0  Description 
0 0 0  8-bit length 
0 0 1 5-bit length 
0 1 0...

 
7. UART (Async Serial Interface) Registers 
 
7.5.  Receive Data Register/Transmit Data Register (RDR/TDR) 
The Receive and Transmit Data Registers are allocated at the same address. This register 
functions as the Receive Data Register when data is read from it. This register operates as 
the Transmit Data Register when data is written in it. 
When FIFO operation is enabled, the RDR/TDR address functions as the FIFO read/write 
address. 
 Receive Data Register (RDR) 
 
bit 15 ... 98 7 6 5 4 3 2 1 0...

 
7. UART (Async Serial Interface) Registers 
 
 Transmit Data Register (TDR) 
 
bit 15 ... 98 7 6 5 4 3 2 1 0 
Field  D8 D7 D6 D5 D4 D3 D2 D1 D0 
Attribute      W W W W W  W W W W 
Initial 
value     1  1 
1 1 1 1 1 1 1 
 
The Transmit Data Register (TDR) is a 9-bit data buffer register for serial data transmission. 
   If data transmission is enabled (SCR:TXE=1 ) and if the transmit data is written in the Transmit Data 
Register (TDR), the transmit data is transferred to  the Transmit Shift Register....

 
7. UART (Async Serial Interface) Registers 
 
7.6.  Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) 
Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency 
division ratio of serial clocks. Also, an external clock can be selected as the clock source of 
the reload counter. 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field EXT (BGR1) (BGR0) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
   The...

 
7. UART (Async Serial Interface) Registers 
 
   Data must be written in the Baud Rate Generator  Registers (BGR1 and BGR0) by 16-bit
  data accessing. 
   If the current values of Baud Rate Generator Registers (BGR1, BGR0) are changed, the new values are 
reloaded only after the counter value has reached 15h00. In order to validate the new set values 
immediately, change the BGR1/0 set values  and execute the programmable clear (UPCL). 
   If the reload value is an even number, in the receive...

 
7. UART (Async Serial Interface) Registers 
 
7.7.  FIFO Control Register 1 (FCR1) 
The FIFO Control Register (FCR1) is used to set the FIFO test, select the transmit or receive 
FIFO, enable the transmit FIFO interrupt, and control the interrupt flag. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field FTST1 FTST0 - FLSTEFRIIEFDRQFTIE FSEL (FCR0) 
Attribute  R/W R/W  - R/W R/W  R/W R/W R/W    
Initial 
value  0 0 - 0 0 1 0 0    
 
[bit 15:14] FTST1, FTST0: FIFO test bits  They are FIFO Test bits. 
They must...

 
7. UART (Async Serial Interface) Registers 
 
[bit 11] FRIIE: Receive FIFO idle detection enable bit This bit sets to detect the receive id le state if the receive FIFO contains  valid data and if it continues more 
than 8-bit hours. If the r eceive interrupt is enabled (SCR:RIE=1), a  receive interrupt is generated when the 
receive idle state is detected. 
If set to 0, a detection of receive idle state is disabled. 
If set to 1, a detection of receive idle state is enabled. 
Bit Description 
0...