Fujitsu Series 3 Manual

 
3. CSIO (Clock Sync Serial  Interface) operations 
 
  Continuous data transmit or receive waiting 
If anything other than (ESCR:WT1, ESCR.WT0)=(0, 0) is set for the continuous data transmission or 
reception, a wait is inserted between frames. 
 
- ESCR.WT1=0, ESCR.WT0=1 (in master mode operation)
SCK
1Byte 2Byte1bit
- ESCR.WT1=1, ESCR.WT0=0 (in master mode operation) SCK
1Byte 2Byte2bit
- ESCR.WT1=1, ESCR.WT0=1 (in master mode operation)
SCK
1Byte 2Byte3bit
TDRE
TDRE
TDRE
 
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3. CSIO (Clock Sync Serial  Interface) operations 
 
  Slave mode operation (Set SCR:MS=1 and SMR:SCKE=0.)  
  Data transmission 
1.  If serial data output is enabled (SMR:SOE=1) and  data transmission is enabled (SCR:TXE=1) and when 
the transmit data is written in the TDR, the SSR:TDRE b it is set to 0. This causes the first bit to output. 
Then, the transmit data is output in synchronization with a rising edge of the serial clock (SCK) output. 
2.  When the first bit of transmit data is output,...

 
3. CSIO (Clock Sync Serial  Interface) operations 
 
3.4.  SPI transfer (II) 
  Features 
 Item  Description 
1 Serial clock (SCK) signal detect level  LOW 
2 Transmit data output timing  SCK signal falling edge   
3 Receive data sampling  SCK signal rising edge 
4 Data length  5 to 9 bits 
 Register settings 
The register values required for SPI data tr ansfer (II) are listed on the table below. 
Table 3-4 SPI transfer (II) register settings 
 Bit 15  Bit 14  Bit 13Bit 12  Bit 11 Bit 10 Bit 09Bit 08...

 
3. CSIO (Clock Sync Serial  Interface) operations 
 
  SPI transfer (II) timing chart 
 
  

Datatransmission
SCK
 
SOUT  
TDR RW
TXE 
 Data reception  
SIN  
RXE  
Sampling
1st byte
RDRF  
TDRE 
2nd byte
RDR RD  
*A 
*B 
D7  
D0   D7
D1  D2D3 D4D5D6 D0D1D2D3D4D5 D6 
D7
D0 D7
D1  D2 D3 D4 D5D6 D0D1 D2 D3D4 D5 D6
* A :  During slave mode transmission (MS=1, SOE=1),  4 machine cycles or more time is required 
after writing data in the TDR .
*
 B :  HIGH if SCR:MS=0 
D0 of the 3rd byte if SCR:MS=1 and...

 
3. CSIO (Clock Sync Serial  Interface) operations 
 
  Master mode operation (Set  SCR:MS=0 and SMR:SCKE=1.) 
  Data transmission 
1.  If serial data output is enabled (SMR:SOE=1), da ta transmission is enabled (SCR:TXE=1) and data 
reception is disabled (SCR:RXE=0),  and when the transmit data is written in the TDR, the SSR:TDRE 
bit is set to 0. This causes the transmit data to be output in synchronization with a falling edge of the 
serial clock (SCK) output. 
2.  The SSR:TDRE bit is set to 1...

 
3. CSIO (Clock Sync Serial  Interface) operations 
 
  Continuous data transmit or receive waiting 
If anything other than (ESCR:WT1, ESCR.WT0)=(0, 0) is set for the continuous data transmission or 
reception, a wait is inserted between frames. 
 
- ESCR.WT1=0, ESCR.WT0=1 (in master mode operation)
SCK
1Byte 2Byte1bit
- ESCR.WT1=1, ESCR.WT0=0 (in master mode operation) SCK
1Byte 2Byte2bit
- ESCR.WT1=1, ESCR.WT0=1 (in master mode operation)
SCK
1Byte 2Byte3bit
TDRE
TDRE
TDRE
 
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3. CSIO (Clock Sync Serial  Interface) operations 
 
  Slave mode operation (Set SCR:MS=1 and SMR:SCKE=0.) 
  Data transmission 
1.  If serial data output is enabled (SMR:SOE=1) and  data transmission is enabled (SCR:TXE=1) and when 
the transmit data is written in the TDR, the SSR:TDRE b it is set to 0. This causes the first bit to output. 
Then, the transmit data is output in synchronization w ith a falling edge of the serial clock (SCK) input. 
2.  When the first bit of transmit data is output,...

 
4. Dedicated baud rate generator 
 
4.  Dedicated baud rate generator 
The dedicated baud rate generator functions in the master mode operation only. However, if 
receive FIFO is used, set the dedicated baud rate generator in the slave mode operation, too. 
  CSIO (Clock Sync Serial In terface) baud rate selection 
The dedicated baud rate generator settings vary depending on the master or slave mode operation. 
[1] During master mode operation 
  Divide the internal clock frequency us ing the...

 
4. Dedicated baud rate generator 
 
4.1.  Baud rate settings 
This section explains how to set the baud rate. Also, the calculation result of serial clock 
frequency is shown. 
  Calculating the baud rate 
Two 15-bit reload counters are set using the Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). 
The baud rate is obtained in the following formulas. 
(1) Reload value 
 
  (2) Calculation example 
To set the 16MHz bus clock, use the internal clock, and set the 19200-bps baud rate, set the...

 
4. Dedicated baud rate generator 
 
  Reload values and baud rates for each bus clock frequency 
Table 4-1 Reload values and baud rates 
8 MHz  10 MHz  16 MHz 20 MHz  24 MHz  32 MHz Baud rate 
(bps) 
Value ERRValue ERR ValueERRValueERRValueERR Value ERR
8 M  - -  - - - - - -  - - 3 0 
6 M  - -  - - - - - - 3 0  - - 
5 M  - -  - - - - 3 0  - -  - - 
4 M - - -  - 3 0  4 0  5 0 7 0 
2.5 M - -  3 0  - -  - -  - - - - 
2 M 3 0  4 0 7 0  9 0 11 0 15  0 
1 M  7 0 9  0 15 0  19 0  23 0 31 0 
500000 15 0  19 0...