Fujitsu Series 3 Manual

 
7. UART (Async Serial Interface) Registers 
 
[bit 8] FSEL: FIFO select bit This bit selects the tr ansmit or receive FIFO. 
If set to 0, transmit FIFO is assigned FIFO 1, and the receive FIFO is assigned FIFO2. 
If set to 1, transmit FIFO is assigned FIFO 2, and the receive FIFO is assigned FIFO1. 
Bit Description 
0 Transmit FIFO:FIFO1; Receive FIFO:FIFO2 
1 Transmit  FIFO:FIFO2; Receive FIFO:FIFO1 
 
 
  This bit  is 

not cleared by the  FIFO Reset (FCR0:FCL2, FCL1 =1). 
   T

o change this bit...

 
7. UART (Async Serial Interface) Registers 
 
7.8.  FIFO Control Register 0 (FCR0) 
The FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, 
save the read pointer, and set the data re-transmission. 
 bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (FCR1) - FLSTFLD FSETFCL2FCL1 FE2 FE1 
Attribute      -  R R/W  R/W R/W R/W  R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] Unused bit  When read, always 0 is read. 
When written, always set this bit to 0. 
 
[bit 6] FLST:...

 
7. UART (Async Serial Interface) Registers 
 
[bit 5] FLD: FIFO pointer reload bit This bit reloads the data, being saved in transmit FIFO by  the FSET bit, to the reload pointer. This bit can be 
used to re-transmit data after a communication error or others have occurred. 
When the re-transmission setting has finished, this bit is set to 0. 
Bit Description 
0 Not  reloaded 
1 Reloaded 
 
 
  If this  b

it is 1, data is being reloaded in the read  point
 er. Therefore, data writing except for FIFO...

 
7. UART (Async Serial Interface) Registers 
 
[bit 3] FCL2: FIFO2 reset bit This bit resets the FIFO2 value. 
If this bit is set to 1, the FIFO2 internal state is initialized. 
Only the FCR1:FLST bit is initialized, and th e other bits of FCR1/0 registers are kept. 
Description Bit 
During writing During reading 
0 No  effect. 
1 FIFO2 is reset.  0 is always read. 
 
 
  Disable the tra n

smission and receptio n first, and then reset FIFO2. 
   Set the tran sm

it FIFO interrupt enable bit to 0...

 
7. UART (Async Serial Interface) Registers 
 
[bit 1] FE2: FIFO2 operation enable bit This bit enables or disables the FIFO2 operation. 
  To use the FIFO2 operation,  set this bit to 1. 
   If FIFO2 is set as transmit FIFO (FCR1:FSEL=1) and if  data exists in FIFO2 when this bit is set to 1, 
the data transmission starts immediately when th e UART is enabled to transmit data (SCR:TXE=1). 
During this time, set both SCR:TIE bit and SCR:TBIE bit to 0. Then, set this bit to 1 and set both 
SCR:TIE bit...

 
7. UART (Async Serial Interface) Registers 
 
7.9.  FIFO Byte Register (FBYTE) 
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. Also, 
this register can be used to generate a receive interrupt when certain number of data sets are 
received in the receive FIFO. 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field (FBYTE2) (FBYTE1) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
The FBYTE...

 
7. UART (Async Serial Interface) Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: UART (Async Serial Interface) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  56 
 
   Set 0x00 in the FBYTE register of transmit FIFO. 
   Set a data value equal to or greater than  2 in the FBYTE register of receive FIFO. 
   This state can be changed only after the data reception has been disabled. 
   A read-modify-write instruction cannot be used for this register. 
   Any setting exceeding the FIFO  capacity is...

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
852 
MB9Axxx/MB9Bxxx  Series  

 
1. Outline of CSIO (Clock Sync Serial Interface) 
 
Chapter: CSIO (Clock Sync Serial Interface) 
This chapter explains the Clock Sync Serial Interface (CSIO) function that is supported in 
Operation mode 2. This CSIO is a part of the multifunction serial interface functions. 
 
1.
 Outline of CSIO (Clock Sync Serial Interface) 
2. CSIO (Clock Sync Serial Interface) interrupts 
3. CSIO (Clock Sync Serial Interface) operations 
4. Dedicated baud rate generator 
5. CSIO (Clock Sync Serial Interface)...

 
1. Outline of CSIO (Clock Sync Serial Interface) 
 
1.  Outline of CSIO (Clock Sync Serial Interface) 
The CSIO is a generic serial data communication interface (supporting the SPI) to allow 
synchronous communication with an external device. It also has transmit/receive FIFO (up to 
128 × 9 bits each) *1installed. 
  CSIO (Clock Sync Serial  Interface) functions 
 
   Function 
1 Data buffer 
  Full duplex double buffer (when FIFO is not used) 
   Transmit/Receive FIFO (up to 128 × 9 bits each) *1...