Fujitsu Series 3 Manual

 
2. CSIO (Clock Sync Serial Interface) interrupts 
 
2.  CSIO (Clock Sync Serial Interface) interrupts 
The CSIO interrupts contain the receive interrupt and the transmit interrupt. These interrupt 
requests can be generated if: 
- A receive data is set in the Receive Data Register (RDR) or a data receive error occurs. 
- A transmit data is transferred from the Transmit Data Register (TDR) to the transmit shift 
register and the data transmission is started 
- The transmit bus is idle (No data...

 
2. CSIO (Clock Sync Serial Interface) interrupts 
 
2.1.  Receive interrupt and flag set timing 
Data reception can be interrupted by a Receive Completion (SSR:RDRF) or a Receive Error 
Occurrence (SSR:ORE). 
  Receive interrupt and flag set timing 
When the last data bit is detected, the received data is  stored in the Receive Data Register (RDR). When the 
data reception is completed (SSR:RDRF=1) or when a  data receive error occurs (SSR:ORE=1), each flag is 
set. If a receive interrupt is enabled...

 
2. CSIO (Clock Sync Serial Interface) interrupts 
 
Figure 2-2 ORE (Overrun Error) flag set timing 
 
SCK
SIN
Receive data 
sampling D0
RDRF
An overrun error occurred.
ORE
Note:
This figure shows the signal timing under the 
following conditions.
SCR: MS=1, SPI=0
ESCR: L2 to L0=0b000
SMR:SCINV=0, BDS=0, SCKE=0, SOE=0
Precautions:
If the next data is transferred be fore the receive data is read (RDRF=1), an overrun error occurs.
D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
  
 
 
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2. CSIO (Clock Sync Serial Interface) interrupts 
 
2.2.  Interrupt occurrence and flag set timing when receive 
FIFO is used 
If receive FIFO is used, an interrupt occurs when the FBYTE data (preset for the FBYTE 
register (FBYTE)) is received. 
 Receive interrupt and flag set ti ming when receive FIFO is used 
If receive FIFO is used, an interrupt occurs de pending on the value set for the FBYTE register. 
   When full FBYTE data is received, the receive data full flag (SSR:RDRF) of the Serial...

 
2. CSIO (Clock Sync Serial Interface) interrupts 
 
Figure 2-4 ORE (Overrun Error) flag bit set timing 
 
Receive data
FIFOBYTE 
(Receive)
RDRF 1st byte
60
An interrupt occurs when the FIFOBYTE 
(receive data) count +1 matches the 
receive data count.
An overrun error occurred.
SCK
Valid byte display59
ORE
Auxiliary notes:
If the FIFO buffer capacity is displayed by the FIFOBYTE and if the next data is received, an 
overrun error occurs.
This figure shows a case where a 64-byte FIFO capacity is...

 
2. CSIO (Clock Sync Serial Interface) interrupts 
 
2.3.  Transmit interrupt occurrence and flag set timing 
A transmit interrupt occurs if data is transferred from the Transmit Data Register (TDR) to the 
transmit shift register (SSR:TDRE=1) and it is transmitted, or if no data is transmitted 
(SSR:TBI=1).  
  Transmit interrupt occurrence and flag set timing 
  Transmit data empty flag (SSR:TDRE) set timing 
After data has been transferred from the Transmit Data  Register (TDR) to the transmit...

 
2. CSIO (Clock Sync Serial Interface) interrupts 
 
2.4.  Interrupt occurrence and flag set timing when 
transmit FIFO is used 
When transmit FIFO is used, an interrupt occurs if the buffer contains no data. 
 Transmit interrupt occurrence and flag se t timing when transmit FIFO is used 
  If transmit FIFO contains no data , the FIFO transmit data request bit (FCR1:FDRQ) is set to 1. 
If a FIFO transmit interrupt is enabled (FCR1:FTIE=1), a transmit interrupt occurs. 
   If you have written the...

 
3. CSIO (Clock Sync Serial  Interface) operations 
 
3.  CSIO (Clock Sync Serial Interface) operations 
The clock synchronous data transmission is used. 
3.1.  Normal transfer (I) 
  Features 
 Item  Description 
1 Serial clock (SCK) signal detect level  HIGH 
2 Transmit data output timing  SCK signal falling edge 
3 Receive data sampling  SCK signal rising edge 
4 Data length  5 to 9 bits 
 Register settings 
The register values required for normal data  transfer (I) are listed on the table below....

 
3. CSIO (Clock Sync Serial  Interface) operations 
 
  Normal transfer (I) timing chart 
 
   *
A 
D7

 Data transmission  
SCK  
SOUT  
TDR RW
TXE  D0D
7
D1 D2 D3 D4 D5 D6
 Data reception  
SIN  
RXE  
Sampling  
1st byte
RDRF 
TDRE 
D0D1 D2D3 D4 D 5   D6  
2nd byte
 
RDR RD  
D7 
D0   D7
D1  D2 D3D4D5D6 D0D1 D2D3 D
 4
D5 D6
D7 value if SCR:MS=1 HIGH if SCR:MS=0
:  
* A
 
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CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
863...

 
3. CSIO (Clock Sync Serial  Interface) operations 
 
  Master mode operation (SCR:MS=0, SMR:SCKE=1) 
  Data transmission 
1.  If serial data output is enabled (SMR:SOE=1), da ta transmission is enabled (SCR:TXE=1) and data 
reception is disabled (SCR:RXE=0),  and when the transmit data is written in the TDR, the SSR:TDRE 
bit is set to 0. This causes the transmit data to be output in synchronization with a falling edge of the 
serial clock (SCK) output. 
2.  When the transmit data of the first bit is...