Fujitsu Series 3 Manual

 FUJITSU SEMICONDUCTOR LIMITED 
 If FIFO is used 
Figure 6-3 An example flowchart for master/slave type communications (if FIFO buffer is used) 
 
(Master CPU)
Start
Set the operation mode.
(Set to mode 1.)
- Enable the transmit/
receive FIFO.
- Setting FBYTE 
No
Set the AD bit to 1.
Set the AD bit to 0.
Read and process  the FBYTE data.
Set the D8 bit to 0.  
Yes (Slave CPU)
Start
Set the operation mode. (Set to mode 1.)
RDRF=1
Set FBYTE to N.
AD = 1 and the 
slave address  match.
No
No
Yes
Yes
Set a...

 
7. UART (Async Serial Interface) Registers 
 
7.  UART (Async Serial Interface) Registers 
This section provides a list of UART (Async Serial Interface) registers. 
 UART (Async Serial Interface) registers list 
 
Table 7-1 UART (Async Serial Interface) register list 
 bit 15                           bit 8bit 7                            bit 0
SCR (Serial Control Register)  SMR (Serial Mode Register) 
SSR (Serial Status Register) ESCR (Extended Communication Control Register)
TDR1/RDR1...

 
7. UART (Async Serial Interface) Registers 
 
7.1.  Serial Control Register (SCR) 
The Serial Control Register (SCR) can perform transmit/receive enable/disable, 
transmit/receive interrupt enable/disable, transmit bus idle interrupt enable/disable and UART 
reset operations. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field UPCL - - RIE TIE TBIE RXE TXE (SMR) 
Attribute  R/W - - R/W R/W  R/W R/W R/W    
Initial 
value  0 - - 0 0 0 0 0    
 
[bit 15] UPCL: Programmable Clear bit  Initializes the UART internal...

 
7. UART (Async Serial Interface) Registers 
 
[bit 12] RIE: Receive interrupt enable bit   This bit enables or disables an output  of receive interrupt request to the CPU. 
   If the RIE bit and the receive data flag bit (SSR:RDRF) are 1, or if any of the  error flag bits (SSR:PE, 
ORE or FRE) is 1, a receive  interrupt request is output. 
 
Bit Description 
0  Disables the receive interrupt. 
1  Enables the receive interrupt. 
 
[bit 11] TIE: Transmit interrupt enable bit    This bit enables or...

 
7. UART (Async Serial Interface) Registers 
 
[bit 8] TXE: Transmit operation enable bit Enables or disables UART transmit operation. 
  If set to 0, transmit operation is disabled. 
   If set to 1, transmit operation is enabled. 
 
Bit Description 
0  Disables the transmission. 
1  Enables the transmission. 
 
 
If data  t

ransmission is disabled (TXE=0), the current data transmission is stopped immediately. 
  
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-2: UART  \050Async  Serial Interface\051...

 
7. UART (Async Serial Interface) Registers 
 
7.2.  Serial Mode Register (SMR) 
The Serial Mode Register (SMR) is used to set operation mode, transfer direction data length 
and to select the stop bit length as well as to enable/disable output of serial data to their pins. 
 bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SCR) MD2 MD1 MD0 WUCRSBL BDS - SOE 
Attribute     R/W R/W R/W  R/W R/W R/W  - R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7:5] MD2, MD1, MD0: Operation mode set bit  Sets operation mode of...

 
7. UART (Async Serial Interface) Registers 
 
[bit 4] WUCR: Wake-up control bit Selects a pin to be used for an external interrupt. 
If set to 0, the INT pin is set as an external interrupt pin. 
If set to 1, the SIN pin is set as an external interrupt pin. 
Bit Description 
0  Disables the Wake-up function. 
1  Enables the Wake-up function. 
 
[bit 3] SBL: Stop bit length select bit  This bit sets a stop bit length (the frame end mark of the transmit data). 
If set to SBL=0 and ESCR:ESBL=0, the stop...

 
7. UART (Async Serial Interface) Registers 
 
[bit 0] SOE: Serial data output enable bit This bit enables or disables a serial data output. 
Bit Description 
0  Disables a serial data output. 
1  Enables a serial data output. 
 
 
If this  b

it is used as the SOUT pin, the GPIO must also be set. 
  
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-2: UART  \050Async  Serial Interface\051 
MN706-00002-1v0-E 
832 
MB9Axxx/MB9Bxxx  Series  

 
7. UART (Async Serial Interface) Registers 
 
7.3.  Serial Status Register (SSR) 
The Serial Status Register (SSR) is used to check the current transmission/reception state, 
check the receive error flag, and clears the receive error flag. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field REC - PE FRE ORE RDRFTDRETBI (ESCR) 
Attribute  R/W - R R  R R R R    
Initial 
value  0 - 0 0 0 0 1 1    
 
[bit 15] REC: Receive error flag clear bit  This bit clears the PE, FRE and ORE flags  of the Serial Status...

 
7. UART (Async Serial Interface) Registers 
 
[bit 12] FRE: Framing error flag bit   If a framing error occurs during data reception, this b it is set to 1. This is cleared if the REC bit of 
Serial Status Register (SSR) is set to 1. 
   If the FRE bit and SCR:RIE bit are 1, a receive interrupt request is output. 
   If this flag is set, data in the R eceive Data Register (RDR) is invalid. 
   If this flag is set when receive FIFO is used, the recei ve FIFO enable bit is cleared and the receive...