Fujitsu Series 3 Manual

 
5. Registers 
 
[bit 11] ESCE: External trigger analog input selection bit This bit selects whether the external trigger analog input is selected with the P1A [2:0] bits in the Priority 
Conversion Input Selection Register (PCIS)  or the external input pin ECS [2:0] bits. 
Bit Description 
0 The external trigger analog input s are selected with P1A [2:0]. 
1 The external trigger analog inputs are selected with an external input. 
 
 
It is not  p

ossible to change the setting of the ESCE bit during...

 
5. Registers 
 
5.8.  Priority Conversion FIFO Stage Count Setup Register (PFNS) 
The Priority Conversion FIFO Stage Count Setup Register (PFNS) sets up the generation of 
interrupt requests in priority conversion. When the specified count of FIFO stages store A/D 
conversion data, the interrupt request bit (PCIF) is set. 
 
bit 7 6 5 4 3 2 1 0 
Field Reserved TEST [1:0] Reserved PFS [1:0] 
Attribute  - -  R R  - -  R/W R/W 
Initial value  X X X  X X X  0 0 
 
[bit 7:6] Reserved: Reserved bits 
Write...

 
5. Registers 
 
5.9.  Priority Conversion FIFO Data Register (PCFD) 
The Priority Conversion FIFO Data Register (PCFD) consists of four FIFO stages and stores 
analog conversion results. Data can be retrieved sequentially by reading the register. 
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field PD11 PD10 PD9  PD8 PD7 PD6PD5PD4PD3PD2PD1PD0Reserved 
Attribute R R R  R R R R R R R R R R R R R 
Initial 
value  X X X X X X X X X X X X X X X X 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved...

 
5. Registers 
 
[bit 7:5] Reserved: Reserved bits The read value is undefined. 
 
[bit 4:0] PC4:PC0: Conversion input channel bits  The analog input channels corresponding to the conversion result written in PD11 to PD0 are written. 
Settings for channels not defined in the product speci fications are not written. See the specified number of 
the analog input channels in th e Data Sheet of each product. 
Bit [4:0]  Description 
0b00000 ch.0 
0b00001 ch.1 
0b00010 ch.2 
... ... 
0b11101 ch.29 
0b11110...

 
5. Registers 
 
5.10.  Priority Conversion Input Selection Register (PCIS) 
The Priority Conversion Input Selection Register (PCIS) is used to select the analog input 
channels for which priority conversion is performed. For software or timer start at priority level 
2, only one channel can be selected from multiple analog input channels. For external trigger 
start at priority level 1, one channel can be selected from eight channels (ch.0 to ch.7). 
 bit 7 6 5 4 3 2 1 0 
Field P2A [4:0] P1A [2:0]...

 
5. Registers 
 
5.11.  A/D Comparison Value Setup Register (CMPD) 
The A/D Comparison Value Setup Register (CMPD) sets the value to be compared with the 
A/D conversion result. When the conditions set in both this register and the A/D Comparison 
Control Register (CMPCR) are satisfied, the conversion result comparison interrupt request 
bit (CMPIF) in the A/D Control Register (ADCR) is set. 
 bit 31 30 29 28 27 26 25 24 
Field CMAD11CMAD10 CMAD9CMA D8CMAD7CMAD6 CMAD5 CMAD4
Attribute R/W R/W R/W  R/W...

 
5. Registers 
 
5.12.  A/D Comparison Control Register (CMPCR) 
The A/D Comparison Control Register (CMPCR) controls the A/D comparison function. When 
the converted value is compared with the value in the A/D Comparison Value Setup Register 
(CMPD) and the comparison condition in this register is satisfied, the conversion result 
comparison interrupt request bit (CMPIF) in the A/D Control Register (ADCR) is set. 
 bit 7 6 5 4 3 2 1 0 
Field CMPENCMD1 CMD0 CCH [4:0] 
Attribute  R/W R/W R/W  R/W R/W R/W...

 
5. Registers 
 
5.13.  Sampling Time Selection Register (ADSS) 
The Sampling Time Selection Register (ADSS3 to 0) allows you to set the sampling time for 
each bit. Which of the sampling times set in Sampling Time Setup Registers 0 and 1 (ADST0 
and 1) is used is specified in this register.   
 ADSS3 (most significant byte: TS31 to  TS24) and ADSS2 (least significant 
byte: TS23 to TS16) 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field TS31 TS30 TS29 TS28  TS27 TS26TS25TS24TS23TS22TS 21TS20 TS19...

 
5. Registers 
 
5.14.  Sampling Time Setup Register (ADST) 
Sampling Time Setup Registers 0 and 1 (ADST0 and 1) set the sampling times for A/D 
conversion. ADST0 and 1 are provided for setting two sampling times, and which one is used 
is selected in the Sampling Time Selection Register (ADSS3 to 0). 
 ADST0 (most significant byte) 
 
bit 15 14 13 12 11 10 9 8 
Field STX02 STX01 STX00 ST04 ST03 ST02  ST01 ST00 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  1 0 0 0 0 
 
[bit 15:13]...

 
5. Registers 
 
 ADST1 (least significant byte) 
 
bit 7 6 5 4 3 2 1 0 
Field STX12 STX11 STX10 ST14 ST13 ST12 ST11 ST10 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  1 0 0 0 0 
 
[bit 7:5] STX12:STX10: Sampling time N times setting bits  These bits multiply the sampling time set values in the ST14 to ST10 bits by N. 
Bit 7  Bit 6 Bit 5  Description 
0 0 0 Set value x 1 
0  0 1 Set value x 4 
0  1 0 Set value x 8 
0  1 1 Set value x 16 
1  0 0 Set value x 32 
1  0 1 Set value x 64...