Fujitsu Series 3 Manual

 
5. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: 10-bit A/D Converter 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  46 
5.15.  Comparison Time Setup Register (ADCT) 
The Comparison Time Setup Register (ADCT) sets the comparison time, which is part of the 
A/D conversion time. 
  bit 15 14 13 12 11 10 9 8 
Field Reserved CT2 CT1 CT0 
Attribute  - - -  - - R/W R/W R/W 
Initial value  X X X  X X 1 1 1 
 
[bit 15:11] Reserved: Reserved bits 
Write Has no effect on operation. 
Read The value is undefined....

 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
736 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
Chapter: 12-bit A/D Converter 
This chapter explains the functions and operations of the 12-bit A/D converter. 
 
1.
 Overview 
2. Configuration 
3. Explanation of Operations 
4. Setup procedure examples 
5. Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFBAD12M3-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-3: 12-bit  A/D Converter 
MN706-00002-1v0-E 
737 
MB9Axxx/MB9Bxxx  Series  

 
1. Overview 
 
1. Overview 
The 12-bit A/D converter is a function that converts analog input voltages into 12-bit digital 
values using a type of the RC Successive Approximation Register. 
 Features of the 12-bit A/D converter 
  12-bit resolution 
   Converter using a type of RC Successive Approximation Register with sample and hold circuits 
   Conversion time of 1.0  s (at a base clock (HCLK) frequency of 72 MHz) 
   Two sampling times selectable for each input channel 
   Scan conversion...

 
2. Configuration 
 
2. Configuration 
This section provides the configuration of the 12-bit A/D converter. 
 12-bit A/D converter block diagram 
Figure 2-1 12-bit A/D converter block diagram 
 
Control unit
A/D converter
Channel & status control unit
Peripheral buses
Buffer
Scan conversion FIFO, 16 
stages  
Priority conversion FIFO, 4  stages
D/A converter  
Comparator  
Sample 
& 
holdAnalog input n
Analog input n-1 ･
･
･
･
Analog input 3
Analog input 2
Analog input 1
Analog input 0
A/D conversion...

 
3. Explanation of Operations 
 
3.  Explanation of Operations 
This chapter explains the operations of the 12-bit A/D converter. 
 
3.1 Enabling operations of the A/D converter 
3.2  A/D conversion operation 
3.3  FIFO operations 
3.4  A/D comparison function 
3.5  Starting DMA 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-3: 12-bit  A/D Converter 
MN706-00002-1v0-E 
740 
MB9Axxx/MB9Bxxx  Series  

 
3. Explanation of Operations 
 
3.1.  Enabling operations of the A/D converter 
This section explains enabling operations of the A/D converter 
The A/D converter must be in the operation enable state prior to A/D conversion. Writing 1 to the ENBL 
bit of the ADCEN register turns the A/D converter from  the operation stop state to the operation enable state 
after the period of operation enable state transitions. On  the other hand, writing 0 to the ENBL bit of the 
ADCEN register turns the A/D...

 
3. Explanation of Operations 
 
3.2. A/D conversion operation 
The A/D converter can perform two types of conversion processes: scan conversion and 
priority conversion. 
 
3.2.1 Scan conversion operation 
3.2.2  Priority conversion operation 
3.2.3  Priority levels and state transitions 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-3: 12-bit  A/D Converter 
MN706-00002-1v0-E 
742 
MB9Axxx/MB9Bxxx  Series  

 
3. Explanation of Operations 
 
3.2.1. Scan conversion operation 
This section explains the scan conversion operation. 
The input channels are selected in the Scan Conversion Input Selection Register (SCIS). By setting the 
corresponding bit in the SCIS to 1, any necessary channel can be selected from among multiple analog 
input channels. 
The A/D converter can be started by software or a timer. To start the converter by software, set the SSTR bit 
in the SCCR register to 1. Then conversion starts. To...

 
3. Explanation of Operations 
 
3. One-shot mode for multiple channels 
This mode is selected when mul tiple analog channels are specified  for scan conversion and RPT = 0 
in the SCCR register. When the conversion starts,  the existence of each channel is automatically 
checked. While the channels are sw itched from one to another, A/D conversion is started and the 
conversion result is written to FIFO when the conversion is completed. The conversion channels are 
selected in descending order of...